Intel might be the key to re-realizing the American dream of advanced chip production and packaging on U.S. soil. Under the Trump administration, the United States has been making significant efforts to establish leading-edge chip manufacturing domestically. Achieving this goal is challenging for several reasons. In the race for the most advanced silicon, only a few major veteran players remain: Intel, Samsung, and TSMC. Among these, Taiwan-based TSMC has consistently overcome obstacles to become the leader in the semiconductor industry. Through a strategic approach to semiconductor development, TSMC has excelled in both leading-edge node production and advanced chip packaging, enhancing performance.

Historically, Intel has faced difficulties with leading-edge semiconductor node production, even outsourcing some chip manufacturing to TSMC. However, there is a significant opportunity for Intel to not only produce silicon but also establish itself as a major packaging partner for many manufacturers, including TSMC. TSMC's facilities in Arizona address the issue of USA-based manufacturing only partially. While TSMC's Arizona Fab 21 produces 4 nm wafers, these wafers must be sent back to Taiwan for packaging, disrupting the sovereign supply chain that is crucial for domestic manufacturing. Addressing these issues could present a good opportunity for Intel, even if Team Blue doesn't manufacture the underlying silicon.Traditionally, Intel has relied on its global sites, such as the Pelican plant in Malaysia, for some of its packaging designs. However, starting in early 2024, Intel expanded its New Mexico facilities to accommodate more advanced packaging capabilities, establishing a true independence layer. The Fab 9 and Fab 11x facilities in Rio Rancho are the first to mass-produce Intel's 3D advanced packaging technology. This site is also Intel's first high-volume advanced packaging facility that is co-located, enabling a complete manufacturing process and creating a more efficient supply chain from demand to finished product.

Enter Intel Foundry's Advanced Packaging Services
Intel's Foundry advanced packaging portfolio allows designers to use 2D, 2.5D, and 3D building blocks to optimize cost, power, and bandwidth at the system level. EMIB is a substrate-embedded silicon bridge that provides localized, high-density die-to-die routing without the cost and area penalty of a full-size silicon interposer. For instance, small silicon EMIB bridges—available in variants like EMIB-M with embedded MIM capacitors, and EMIB-T with TSVs—provide low-cost, high-density shoreline connections ideal for logic-to-logic and logic-to-HBM interfaces. Additionally, the Foveros family, including Foveros-S, R, B, and Foveros Direct, offers interposer and RDL options along with true 3D stacking using Cu-to-Cu hybrid bonding, for scenarios requiring extreme die-to-die bandwidth or power efficiency.

These variants of EMIB are giving flexibility to every chip designer, depending on the type of package. Overcoming the full reticle size of 830 mm² is possible with the use of EMIB, so ASIC designers can choose designs that are as complex as Intel's "Ponte Vecchio," which uses EMIB 3.5D for more than 100 billion transistors, 47 active tiles, and five process nodes combined on a single chip. The sheer complexity of this product—powering the Exascale supercomputer Aurora—demonstrated that Intel was able to deliver a product with the world's most advanced packaging in a mission-critical environment. This proved that advanced packaging stores a completely separate value inside Intel Foundry.On the topic of silicon, Intel's 18A node and its future variations, 18A-P and 18A-PT, are going to be long-lived nodes inside Intel facilities. At the recent Q3 earnings call, CFO David Zinsner stated: "We are not at peak supply for 18A. In fact, we don't get there until the end of the decade. We do think that this node will be a fairly long-lived node for us. We will continue to make investments on 18A over time." This continued investment will drive yield, as well as variations of the 18A node adapted for designs from mobile to HPC and AI. This demonstrates that Intel has strategically invested over the years to ensure sufficient capacity. Even with the addition of new customers, there will still be enough 18A wafer supply to meet Intel's own product portfolio goals while also providing a reliable supply for external customers.

However, a real advantage for Intel nodes begins with 14A, which is industry's first High-NA EUV design. Intel has reported processing over 30,000 wafers in a single quarter using High-NA EUV exposure, achieving simplified manufacturing by reducing the required steps for a particular layer from 40 to fewer than 10, which has led to faster cycle times. Additionally, at this stage of development, 14A is reaching better milestones than 18A. This has been done in coordination with external partners to ensure that when the 14A node goes into volume production, everything will be ready for smooth integration and manufacturing.

Completing the entire semiconductor manufacturing process is a complex task. Although TSMC can provide advanced—but not its most advanced—manufacturing capabilities in the USA, packaging remains a challenge. To address this, TSMC plans to collaborate with Amkor, which is constructing a $7 billion facility in Arizona focused on advanced outsourced semiconductor packaging and testing. This partnership will enable TSMC to outsource packaging to Amkor's Arizona facility, allowing chips produced at the nearby TSMC Fab 21 to be packaged there. Amkor aims to finish the new site by mid-2027, with production set to begin in early 2028. In the meantime, Intel can offer its advanced EMIB packaging to partners, even TSMC's customers, who could be using these advanced packaging techniques to build a competitive product. The only question that remains is how far is Intel willing to push its external packaging business, without obliging customers to its 18A and 14A nodes.