TSMC has reportedly achieved near-perfect packaging yields, establishing a baseline of about 98% for its current CoWoS advanced packaging. This technology accommodates a die area equivalent to 5.5 times the reticle limit, or about 858 mm². As a result, packaging 4,720 mm² worth of silicon on CoWoS-L is now possible, with only 1-2% of the packaged designs experiencing issues. This is a significant achievement for a packaging technology that went into mass production earlier this year. Although CoWoS-L has been shipping for some time, this year marks the first time a 5.5x reticle chip has been packaged on a mass production scale.

The Taiwanese manufacturing giant is also preparing for even larger designs, including up to 14x reticle size dies on a single, enormous package. This means a silicon area of 12,012 mm² will be packaged using TSMC's CoWoS, or specifically one of its variants. This technology is slated for 2029, when its A13 node is expected to be in mass production. TSMC's timelines are consistently being met with customer satisfaction, and the company continues to sell out its manufacturing and advanced packaging technologies. However, creating any design beyond the 3x reticle limit must be done carefully, as thermal warping can introduce mechanical issues. The company is constantly working with customers to overcome these challenges.In addition to CoWoS, TSMC is actively advancing its SoIC hybrid bonding technology. The SoIC 6-micron hybrid bonding pitch entered high-volume production last year and is expected to be reduced to 4.5 microns by 2029, with the capability to stack A14 chips. SoIC can achieve over 50 times the interconnect density and five times the energy efficiency compared to standard designs, making it one of the packaging alternatives that TSMC offers.