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Intel Zooms in on "Lakefield" Foveros Package

The fingernail-size Intel chip with Foveros technology is a first-of-its kind. With Foveros, processors are built in a totally new way: not with the various IPs spread out flat in two dimensions, but with them stacked in three dimensions. Think of a chip designed as a layer cake (a 1-millimeter-thick layer cake) versus a chip with a more-traditional pancake-like design. Intel's Foveros advanced packaging technology allows Intel to "mix and match" technology IP blocks with various memory and I/O elements - all in a small physical package for significantly reduced board size. The first product designed this way is "Lakefield," the Intel Core processor with Intel hybrid technology.

Industry analyst firm The Linley Group recently named Intel's Foveros 3D-stacking technology as "Best Technology" in its 2019 Analysts' Choice Awards. "Our awards program not only recognizes excellence in chip design and innovation, but also acknowledges the products that our analysts believe will have an impact on future designs," said Linley Gwennap, of The Linley Group.

Intel Core i5-L16G7 is the first "Lakefield" SKU Appearance, Possible Prelude to New Nomenclature?

Intel Core i5-L16G7 is the first commercial SKU that implements Intel's "Lakefield" heterogenous x86 processor architecture. This 5-core chip features one high-performance "Sunny Cove" CPU core, and four smaller "Tremont" low-power cores, with an intelligent scheduler balancing workloads between the two core types. This is essentially similar to ARM big.LITTLE. The idea being that the device idles most of the time, when lower-powered CPU cores can hold the fort; performance cores kick in only when really needed, until which time they remain power-gated. Thai PC enthusiast TUM_APISAK discovered the first public appearance of the i5-L16G7 in an unreleased Samsung device that has the Userbenchmark device ID string "SAMSUNG_NP_767XCL."

Clock speeds of the processor are listed as "1.40 GHz base, with 1.75 GHz turbo," but it's possible that the two core types have different clock-speed bands, just like the cores on big.LITTLE SoCs. Other key components of "Lakefield" include an iGPU based on the Gen11 graphics architecture, and an LPDDR4X memory controller. "Lakefield" implements Foveros packaging, in which high-density component dies based on newer silicon fabrication nodes are integrated with silicon interposers based on older fabrication processes, which facilitate microscopic high-density wiring between the dies. In case of "Lakefield," the Foveros package features a 10 nm "compute field" die sitting atop a 22 nm "base field" interposer.

Microsoft Unveils First Intel "Lakefield" Device and Surface Lineup with 10th Gen Core

Today, at a launch event in New York City, Microsoft previewed the Surface Neo, a category-defining device co-engineered with Intel. The dual-screen device will be powered by Intel's unique processor, code-named "Lakefield," that features an industry-first architecture combining a hybrid CPU with Intel's Foveros 3D packaging technology. It offers device-makers more flexibility to innovate on design, form factor and experience.

"The innovation we've achieved with Lakefield gives our industry partners the ability to deliver on new experiences, and Microsoft's Neo is trailblazing a new category of devices. Intel is committed to pushing the boundaries of computing by delivering key technology innovations for partners across the ecosystem," said Gregory Bryant, Intel executive vice president and general manager of the Client Computing Group.

Intel "Tremont" Low-power CPU to Feature L3 Cache

Intel's next-generation Pentium Silver "Snow Ridge" SoC, featuring "Tremont" CPU cores, could see the debut of an L3 cache to the segment. Intel CPU cores in this segment, such as the "Goldmont Plus," only feature shared L2 caches across 4-core modules. The introduction of L3 cache was indicated by a new performance counter "MEM_LOAD_UOPS_RETIRED_L3_HIT," with a description clearly mentioning a "level 3 cache." The introduction of L3 cache as the SoC's LLC (last level cache) could mean Intel is trying to improve inter-component communication by introducting the L3 cache as "town-square" for the various components of the SoC, such as the CPU cores, the iGPU, and the integrated chipset. The company could deploy a ring-bus interconnect that has ring-stops at the various components, and slices of this L3 cache. Intel is building the "Snow Ridge" silicon on its swanky new 10 nm silicon fabrication process, and the chip could see a 2020 debut targeting network infrastructure devices.

Intel's Next Atom Core, Tremont, Revealed - Likely to Be Fabbed on the 10 nm Process

Intel, via its internal documentation that is, routinely, the source of new information on unreleased products, has revealed their next low-power architecture. Codenamed Tremont, the new architecture is expected to be developed on the company's 10 nm process (not unlike Ice Lake) and bring some performance improvements to the company's options for the embedded market.

Tremont will thus replace Intel's Goldmont Plus, which is still being manufactured on the company's 14 nm process (it hasn't been side-graded to the company's 14 nm + or ++ processes, due to these being less suited for denser chip designs). The new architecture will likely receive some specific performance improvements that mirror some of Intel's Core architecture's improvements, alongside support for new instruction sets - CLWB, GFNI (SSE-based), ENCLV, Split Lock Detection instruction set extensions are all extensions that will also be introduced in the company's Ice Lake cores, which increases the likelihood of the same process. Other functions introduced specifically for Tremont include CLDEMOTE, direct store, and user wait instructions.

Intel Could Develop its own big.LITTLE x86 Adaptation

big.LITTLE is an innovation by ARM, which seeks to minimize power-draw on mobile devices. It is a sort of heterogeneous multi-core CPU design, in which a few "big" high-performance CPU cores work alongside a few extremely low-power "little" CPU cores. The idea here is that the low-power cores consume much lesser power at max load, than the high-performance cores at their minimum power-state, so the high-performance cores can be power-gated when the system doesn't need them (i.e. most of the time).

Intel finds itself with two distinct x86 implementations at any given time. It has low-power CPU micro-architectures such as "Silvermont," "Goldmont," and "Goldmont Plus," etc., implemented on low-power product lines such as the Pentium Silver series; and it has high-performance micro-architectures, such as "Haswell," "Skylake," and "Coffee Lake." The company wants to take a swing at its own heterogeneous multi-core CPU, according to tech stock analyst Ashraf Eassa, with the Motley Fool.
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