Tuesday, November 6th 2018

AMD Unveils "Zen 2" CPU Architecture and 7 nm Vega Radeon Instinct MI60 at New Horizon

AMD today held its "New Horizon" event for investors, offering guidance and "color" on what the company's near-future could look like. At the event, the company formally launched its Radeon Instinct MI60 GPU-based compute accelerator; and disclosed a few interesting tidbits on its next-generation "Zen 2" mircroarchitecture. The Instinct MI60 is the world's first GPU built on the 7 nanometer silicon fabrication process, and among the first commercially available products built on 7 nm. "Rome" is on track to becoming the first 7 nm processor, and is based on the Zen 2 architecture.

The Radeon Instinct MI60 is based on a 7 nm rendition of the "Vega" architecture. It is not an optical shrink of "Vega 10," and could have more number-crunching machinery, and an HBM2 memory interface that's twice as wide that can hold double the memory. It also features on-die logic that gives it hardware virtualization, which could be a boon for cloud-computing providers.
If you've been paying attention to our "Zen 2" coverage over the past couple of weeks, you would've read our recent article citing a Singapore-based VLSI engineer claiming that AMD could disintegrate the northbridge for its high core-count enterprise CPUs, in an attempt to make the memory I/O "truly" wide, without compromising on the idea of MCM CPU chiplets. All of that is true.

"Rome" is codename for a multi-chip module of four to eight 7 nm CPU dies, wired to a centralized die over InfinityFabric. This 14 nm die, called "I/O die," handles memory and PCIe, providing a monolithic 8-channel memory interface, overcoming the memory bandwidth bottlenecks of current-generation 4-die MCMs. The CPU dies and an I/O die probably share an interposer. Assuming each die has 8 CPU cores, "Rome" could have up to 64 cores, an 8-channel DDR4 memory interface, and a 96-lane PCI-Express gen 4.0 root-complex, per socket. If AMD has increased its core-count per CPU die, Rome's core count could be even higher.
The broader memory I/O, assuming InfinityFabric does its job, could significantly improve performance of multi-threaded workloads that can scale across as many cores as you can throw at them, utilizing a truly broader memory interface. AMD also speaks of "increased IPC," which bodes well for the client-segment. AMD has managed to increase IPC (per-core performance), with several on-die enhancements to the core design.

With "Zen" and "Zen+," AMD recognized several components on the core that could be broadened or made faster, which could bring about tangible IPC improvements. This includes a significantly redesigned front-end. Zen/Zen+ feature a front-end that's not much different than AMD's past micro-architectures. The new front-end includes an improved branch-predictor, a faster instruction prefetcher, an improved/enlarged L1 instruction cache, and an improved prefetcher cache (L2).

The number-crunching machinery, the floating point unit, also receives a massive overhaul. "Zen 2" features 256-bit FPUs, which are doubled in width compared to Zen. load/store/dispatch/retire bandwidths have been doubled over the current generation. These changes are massive. Given that even without these core-level changes, by simply improving cache latencies, AMD managed to eke out a ~3% IPC uplift with "Zen+," one can expect double-digit percentage IPC gains with "Zen 2." Higher IPC, combined with possible increased core counts, higher clock speeds, and power benefits of switching to 7 nm, complete AMD's "Zen 2" proposition. Source: Tom's Hardware
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57 Comments on AMD Unveils "Zen 2" CPU Architecture and 7 nm Vega Radeon Instinct MI60 at New Horizon

#51
WikiFM
Mysteoa
Since 7nm has 50% power reduction, adding 50% more cores gets you back to the same power envelope or close to. The other thing you need to consider is ROME has PCIeX 4 and I'm no sure how that will work with the current boards. We know Amd was already working on ROME/ ZEN2 while designing the socket so they could have made it to support 64 cores.
I think that Rome will work at PCI E 3 in current Mobos, if you want PCI E 4 you need a new Mobo. Perhaps 32+ cores CPUs will require a new Mobo too. Could also be that even using same socket there is no compatibility (like 1151, Coffee Lake can't be used in 100 o 200 Mobos).
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#52
RichF
[quote=Wikipedia]The number of instructions executed per clock is not a constant for a given processor; it depends on how the particular software being run interacts with the processor]
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#53
Renald
Can't wait to build my new rig... I'm still with my i7 860 ^^
I have a i7 3770 still in an empty rig, but I'm tired of reinstalling all of my software and configuration...
Posted on Reply
#54
Patriot
Renald
Can't wait to build my new rig... I'm still with my i7 860 ^^
I have a i7 3770 still in an empty rig, but I'm tired of reinstalling all of my software and configuration...
Well... you fixed it one place but not everywhere... 128 lanes of pcie 4 not 96
Posted on Reply
#55
Renald
Patriot
Well... you fixed it one place but not everywhere... 128 lanes of pcie 4 not 96
??? I don't understand your post ... (sry for the dig up)
Posted on Reply
#56
Patriot
Renald
??? I don't understand your post ... (sry for the dig up)
Sry... I clicked reply on the article and it replied on the last post for some reason.
The article has the incorrect amount of pcie lanes. Rome has 128 pcie 4 lanes not 96.
Posted on Reply
#57
Renald
Makes more sense so :p
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