The US government is investigating the potential national security risks associated with China's involvement in the development of open-source RISC-V chip technology. According to a letter obtained by Reuters, the Department of Commerce has informed US lawmakers that it is actively reviewing the implications of China's work in this area. RISC-V, an open instruction set architecture (ISA) created in 2014 at the University of California, Berkeley, offers an alternative to proprietary and licensed ISAs like those developed by Arm. This open-source ISA can be utilized in a wide range of applications, from AI chips and general-purpose CPUs to high-performance computing applications. Major Chinese tech giants, including Alibaba and Huawei, have already embraced RISC-V, positioning it as a new battleground in the ongoing technological rivalry between the United States and China over cutting-edge semiconductor capabilities.

In November, a group of 18 US lawmakers from both chambers of Congress urged the Biden administration to outline its strategy for preventing China from gaining a dominant position in RISC-V technology, expressing concerns about the potential impact on US national and economic security. While acknowledging the need to address potential risks, the Commerce Department noted in its letter that it must proceed cautiously to avoid unintentionally harming American companies actively participating in international RISC-V development groups. Previous attempts to restrict the transfer of 5G technology to China have created obstacles for US firms involved in global standards bodies where China is also a participant, potentially jeopardizing American leadership in the field. As the review process continues, the Commerce Department faces the delicate task of balancing national security interests with the need to maintain the competitiveness of US companies in the rapidly evolving landscape of open-source chip technologies.

Today at Embedded World, SiFive, Inc., the pioneer and leader of RISC-V computing, unveiled its new state-of-the-art RISC-V development board, the HiFive Premier P550. The board will be available for large-scale deployment through Arrow Electronics so developers around the world can test and develop new RISC-V applications like machine vision, video analysis, AI PC and others, allowing them to use AI and other cutting-edge technologies across many different market segments.

With a quad-core SiFive Performance P550 processor, the HiFive Premier P550 is the highest performance RISC-V development board in the industry, and the latest in the popular HiFive family. Designed to meet the computing needs of modern workloads, the out-of-order P550 core delivers superior compute density and performance in an energy-efficient area footprint. Furthermore, the modular design of the HiFive Premier P550, which includes a replaceable system-on-module (SOM) board, gives developers the flexibility they need to tailor their designs.

Imagination Technologies today unveils the next product in the Catapult CPU IP range, the Imagination APXM-6200 CPU: a RISC-V application processor with compelling performance density, seamless security and the artificial intelligence capabilities needed to support the compute and intuitive user experience needs for next generation consumer and industrial devices.

"The number of RISC-V based devices is skyrocketing with over 16Bn units forecast by 2030, and the consumer market is behind much of this growth" says Rich Wawrzyniak, Principal Analyst at SHD Group. "One fifth of all consumer devices will have a RISC-V based CPU by the end of this decade. Imagination is set to be a force in RISC-V with a strategy that prioritises quality and ease of adoption. Products like APXM-6200 are exactly what will help RISC-V achieve the promised success."

While we are all used to having a system with a CPU, GPU, and, recently, NPU—X-Silicon Inc. (XSi), a startup founded by former Silicon Valley veterans—has unveiled an interesting RISC-V processor that can simultaneously handle CPU, GPU, and NPU workloads in a chip. This innovative chip architecture, which will be open-source, aims to provide a flexible and efficient solution for a wide range of applications, including artificial intelligence, virtual reality, automotive systems, and IoT devices. The new microprocessor combines a RISC-V CPU core with vector capabilities and GPU acceleration into a single chip, creating a versatile all-in-one processor. By integrating the functionality of a CPU and GPU into a single core, X-Silicon's design offers several advantages over traditional architectures. The chip utilizes the open-source RISC-V instruction set architecture (ISA) for both CPU and GPU operations, running a single instruction stream. This approach promises lower memory footprint execution and improved efficiency, as there is no need to copy data between separate CPU and GPU memory spaces.

Called the C-GPU architecture, X-Silicon uses RISC-V Vector Core, which has 16 32-bit FPUs and a Scaler ALU for processing regular integers as well as floating point instructions. A unified instruction decoder feeds the cores, which are connected to a thread scheduler, texture unit, rasterizer, clipping engine, neural engine, and pixel processors. All is fed into a frame buffer, which feeds the video engine for video output. The setup of the cores allows the users to program each core individually for HPC, AI, video, or graphics workloads. Without software, there is no usable chip, which prompts X-Silicon to work on OpenGL ES, Vulkan, Mesa, and OpenCL APIs. Additionally, the company plans to release a hardware abstraction layer (HAL) for direct chip programming. According to Jon Peddie Research (JPR), the industry has been seeking an open-standard GPU that is flexible and scalable enough to support various markets. X-Silicon's CPU/GPU hybrid chip aims to address this need by providing manufacturers with a single, open-chip design that can handle any desired workload. The XSi gave no timeline, but it has plans to distribute the IP to OEMs and hyperscalers, so the first silicon is still away.

MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to accelerate ecosystem enablement of MIPS RISC-V IP and their customer's ability to innovate compute without constraints. MIPS will showcase MIPS' RISC-V IP Core technology utilizing the Synopsys ImperasFPM Fast Processor Models and the Synopsys ImperasPDK Processor Development Kit software simulation tools at embedded world 2024.

The MIPS RISC-V P8700 IP featured in the demo at embedded world, is a versatile processor, available in scalable multicore configurations, capable of running Linux and other high-level operating systems (HLOS) and is suitable for a variety of automotive (and non-automotive) applications. As a key benefit, customers using the Synopsys ImperasFPM and ImperasPDK fast simulation solution can get started early with software development for the MIPS P8700 and I8500.

InnoGrit's low-wattage 12 nanometer IG5666 controller popped up on the T-FORCE GE PRO PCIe 5.0 SSD series earlier in the year, but attention has turned to another consumer-grade design. Parent company—Yingren Technology—is not well known outside of China, although its InnoGrit brand has started to make inroads within Western markets. The enterprise-level YRS900 PCIe 5.0 SSD controller was announced last September—this open-source RISC-V-based solution was designed/engineered to "align with U.S. export restrictions." According to cnBeta and MyDrivers reports, a new YRS820 controller has successfully reached the mass production phase. This is a PCIe 5.0 consumer-grade controller, likely derived from its big sibling (YRS900).

According to InnoGrit presentation material, their new model is based on: "RISC-V instruction architecture, adopts a 4-channel PCIe 5.0 interface, is equipped with 8 NAND flash memory channels, supports NVMe 2.0 protocol, has an interface transmission rate of 2667MT/s, can be paired with 3D TLC/QLC, and supports a maximum capacity of up to 8 TB." Company representatives stated that the YRS820 controller is destined to be fitted on high-end consumer parts—the AI PC market segment is a key goal, since the YRS820 is able to: "accelerate data processing for specific applications and have high stability, consistency and security." cnBeta highlighted some anticipated performance figures: "YRS820 achieves sequential read 14 GB/s, sequential write 12 GB/s, random read and random write up to 2000K IOPs and 1500K IOPs respectively." InnoGrit did not reveal a release timetable, since their latest consumer-grade controller is going through a validation process. The company is currently collaborating with domestic NAND flash memory and DRAM manufacturers, as well as other industry bodies.

Chinese e-commerce and cloud giant Alibaba announced its plans to launch a server-grade RISC-V processor later this year, and it showcased a RISC-V-powered laptop running an open-source operating system. The announcements were made by Alibaba's research division, the Damo Academy, at the recent Xuantie RISC-V Ecological Conference in Shenzhen. The upcoming server-class processor called the Xuantie C930, is expected to be launched by the end of 2024. While specific details about the chip have not been disclosed, it is anticipated to cater to AI and server workloads. This development is part of Alibaba's ongoing efforts to expand its RISC-V portfolio and reduce reliance on foreign chip technologies amidst US export restrictions. To complement the C930, Alibaba is also preparing a Xuantie 907 matrix processing unit for AI, which could be an IP block inside an SoC like the C930 or an SoC of its own.

In addition to the C930, Alibaba showcased the RuyiBOOK, a laptop powered by the company's existing T-Head C910 processor. The C910, previously designed for edge servers, AI, and telecommunications applications, has been adapted for use in laptops. Strangely, the RuyiBOOK laptop runs on the openEuler operating system, an open-source version of Huawei's EulerOS, which is based on Red Hat Linux. The laptop also features Alibaba's collaboration suite, Ding Talk, and the open-source office software Libre Office, demonstrating its potential to cater to the needs of Chinese knowledge workers and consumers without relying on foreign software. Zhang Jianfeng, president of the Damo Academy, emphasized the increasing demand for new computing power and the potential for RISC-V to enter a period of "application explosion." Alibaba plans to continue investing in RISC-V research and development and fostering collaboration within the industry to promote innovation and growth in the RISC-V ecosystem, lessening reliance on US-sourced technology.

Tenstorrent and MosChip Technologies announced today that they are partnering on design for Tenstorrent's cutting-edge RISC-V solutions. In selecting MosChip Technologies, Tenstorrent stands to strongly advance both its own and its customers' development of RISC-V solutions as they work together on Physical Design, DFT, Verification, and RTL Design services.

"MosChip Technologies is special in that they have unparalleled tape out expertise in design services, with more than 200 multi-million gate ASICs under their belt", said David Bennett, CCO of Tenstorrent. "Partnering with MosChip enables us to design the strongest RISC-V solution we can to serve ourselves, our partners, and our customers alike."

According to the report from a journal called Fundamental Research, researchers from the Institute of Computing Technology at the Chinese Academy of Sciences have developed a 256-core multi-chiplet processor called Zhejiang Big Chip, with plans to scale up to 1,600 cores by utilizing an entire wafer. As transistor density gains slow, alternatives like multi-chiplet architectures become crucial for continued performance growth. The Zhejiang chip combines 16 chiplets, each holding 16 RISC-V cores, interconnected via network-on-chip. This design can theoretically expand to 100 chiplets and 1,600 cores on an advanced 2.5D packaging interposer. While multi-chiplet is common today, using the whole wafer for one system would match Cerebras' breakthrough approach. Built on 22 nm process technology, the researchers cite exascale supercomputing as an ideal application for massively parallel multi-chiplet architectures.

Careful software optimization is required to balance workloads across the system hierarchy. Integrating near-memory processing and 3D stacking could further optimize efficiency. The paper explores lithography and packaging limits, proposing hierarchical chiplet systems as a flexible path to future computing scale. While yield and cooling challenges need further work, the 256-core foundation demonstrates the potential of modular designs as an alternative to monolithic integration. China's focus mirrors multiple initiatives from American giants like AMD and Intel for data center CPUs. But national semiconductor ambitions add urgency to prove domestically designed solutions can rival foreign innovation. Although performance details are unclear, the rapid progress shows promise in mastering modular chip integration. Combined with improving domestic nodes like the 7 nm one from SMIC, China could easily create a viable Exascale system in-house.

Semiconductor industry players Robert Bosch GmbH, Infineon Technologies AG, Nordic Semiconductor ASA, NXP Semiconductors, and Qualcomm Technologies, Inc., have formally established Quintauris GmbH. Headquartered in Munich, Germany, the company aims to advance the adoption of RISC-V globally by enabling next-generation hardware development.

The formation of Quintauris was formally announced in August, with the aim to be a single source to enable compatible RISC-V-based products, provide reference architectures, and help establish solutions to be widely used across various industries. The initial application focus will be automotive, but with an eventual expansion to include mobile and IoT.

Chinese company Sipeed has introduced the Lichee Pocket 4A, one of the first handheld gaming devices based on the RISC-V open-source instruction set architecture (ISA). Sipeed positions the device as a retro gaming platform capable of running simple titles via software rendering or GPU acceleration. At its core is Alibaba's T-Head TH1520 processor featuring four 2.50 GHz Xuantie C910 RISC-V general-purpose CPU cores and an unnamed Imagination GPU. The chip was originally aimed at laptop designs. Memory options include 8 GB or 16 GB LPDDR4X RAM and 32 GB or 128 GB of storage. The Lichee Pocket 4A has a 7-inch 1280x800 LCD touchscreen, Wi-Fi/Bluetooth connectivity, and an array of wired ports like USB and Ethernet. It weighs under 500 grams. The device can run Android or Linux distributions like Debian, Ubuntu, and others.

As an early RISC-V gaming entrant, performance expectations should be modest—the focus is retro gaming and small indie titles, not modern AAA games. Specific gaming capabilities remain to be fully tested. However, the release helps showcase RISC-V's potential for consumer electronics and competitive positioning against proprietary ISAs like ARM. Pricing is still undefined, but another Sipeed handheld console retails for around $250 currently. Reception from enthusiasts and developers will demonstrate whether there's a viable market for RISC-V gaming devices. Success could encourage additional hardware experimentation efforts across emerging open architectures. With a 6000 mAh battery, battery life should be decent. Other specifications can be seen in the table below, and the pre-order link is here.

Renesas Electronics Corporation, a premier supplier of advanced semiconductor solutions, announced today that it has designed and tested a 32-bit CPU core based on the open-standard RISC-V instruction set architecture (ISA). Renesas is among the first in the industry to independently develop a CPU core for the 32-bit general-purpose RISC-V market, providing an open and flexible platform for IoT, consumer electronics, healthcare and industrial systems. The new RISC-V CPU core will complement Renesas' existing IP portfolio of 32-bit microcontrollers (MCUs), including the proprietary RX Family and the RA Family based on the Arm Cortex -M architecture.

RISC-V is an open ISA which is quickly gaining popularity in the semiconductor industry, due to its flexibility, scalability, power efficiency and open ecosystem. While many MCU providers have recently created joint investment alliances to accelerate their development of RISC-V products, Renesas has already developed a new RISC-V core on its own. This versatile CPU can serve as a main application controller, a complementary secondary core in SoCs, on-chip subsystems, or even in deeply embedded ASSPs. This positions Renesas as a leader in the emerging RISC-V market, following previous introductions of its 32-bit voice-control and motor-control ASSP devices, as well as the RZ/Five 64-bit general purpose microprocessors (MPUs), which were built on CPU cores developed by Andes Technology Corp.

Rapidus Corporation, a company involved in the research, development, design, manufacture, and sales of advanced logic semiconductors, today announced an agreement with Tenstorrent Inc., a next-generation computing company building computers for AI, to jointly develop semiconductor IP (design assets) in the field of AI edge devices based on 2 nm logic semiconductors.

In addition to its AI processors and servers, Tenstorrent built and owns the world's most performant RISC-V CPU IP and licenses that technology to its customers around the world. Through this technological partnership with Rapidus, Tenstorrent will accelerate the development of cutting-edge devices to meet the needs of the ever-evolving digital society.

Synopsys, Inc. (Nasdaq: SNPS) today announced it has extended its ARC Processor IP portfolio to include new RISC-V ARC-V Processor IP, enabling customers to choose from a broad range of flexible, extensible processor options that deliver optimal power-performance efficiency for their target applications. Synopsys leveraged decades of processor IP and software development toolkit experience to develop the new ARC-V Processor IP that is built on the proven microarchitecture of Synopsys' existing ARC Processors, with the added benefit of the expanding RISC-V software ecosystem.

Synopsys ARC-V Processor IP includes high-performance, mid-range, and ultra-low power options, as well as functional safety versions, to address a broad range of application workloads. To accelerate software development, the Synopsys ARC-V Processor IP is supported by the robust and proven Synopsys MetaWare Development Toolkit that generates highly efficient code. In addition, the Synopsys.ai full-stack AI-driven EDA suite is co-optimized with ARC-V Processor IP to provide an out-of-the-box development and verification environment that helps boost productivity and quality-of-results for ARC-V-based SoCs.

Ventana Micro Systems Inc. today announced the second generation of its Veyron family of RISC-V processors. The new Veyron V2 is the highest performance RISC-V processor available today and is offered in the form of chiplets and IP. Ventana Founder and CEO Balaji Baktha will share the details of Veyron V2 today during his keynote speech at the RISC-V Summit North America 2023 in Santa Clara, California.

"Veyron V2 represents a leap forward in our quest to lead the industry in high-performance RISC-V CPUs that are ready for rapid customer adoption," said Balaji Baktha, Founder and CEO of Ventana. "It substantiates our commitment to customer innovation, workload acceleration, and overall optimization to achieve best in class performance per Watt per dollar. V2 enhancements unleash innovation across data center, automotive, 5G, AI, and client applications."

Alibaba's T-Head unit, responsible for the design and development of in-house IC design, has announced the first domestic SSD controller based on the PCIe 5.0 specification standard. Called the Zhenyue 510, the SSD controller is aimed at enterprise SSD offerings. Interestingly, the Zhenyue 510 is powered by T-Head's custom Xuantie C910 cores based on RISC-V instruction set architecture (ISA). Supporting the PCIe 5.0 standard for interfacing, the SSD controller uses DDR5 memory as a cache buffer. Regarding the performance, there are no official figures yet, but the company claims to have 30% lower input/output latencies compared to competing offerings. T-Head claims the SSD has an IO processing capability of "3400 Kilo IOs per second, a data bandwidth of 14 Gbytes/s, and an extremely high energy efficiency of 420 Kilo IO per second for every Watt".

This is an essential step towards Chinese self-sufficiency as T-Head has designed various ICs for processing different tasks. Still, now Alibaba's chip design unit has a domestic design for storage as well. Claiming low latency figures, the Zhenyue 510 is suitable for enterprise workloads like big data analysis, as well as AI inference/training systems workloads. The development of Zhenyue 510 started in 1H 2021, and it took the company more than two years to complete the design and validation of the chip to prepare it for deployment. This is the second Chinese-made SSD controller after Yingren Technology (InnoGrit) announced their chip in September.

BeagleBoard.org, a pioneer in open-source single-board computers (SBCs), is excited to unveil the BeagleV -Fire, a revolutionary SBC powered by the Microchip's PolarFire MPFS025T FCVG484E 5x core RISC-V System on Chip (SoC) with FPGA fabric. This remarkable addition to the BeagleBoard.org BeagleV family of boards opens up new horizons for developers, tinkerers, and the open-source community to explore the vast potential of RISC-V architecture and FPGA technology.

BeagleV -Fire is the second board in the BeagleV series of single board computers (SBCs) from BeagleBoard.org. BeagleV -Fire like other BeagleV SBCs, is set to revolutionize the world of embedded systems and empower developers and enthusiasts worldwide. After the launch of BeagleV -Ahead, BeagleV -Fire represents another significant milestone in the democratization of computer architecture and open-source hardware development for the masses. Built around the powerful and energy-efficient RISC-V instruction set architecture (ISA) along with its versatile FPGA fabric, BeagleV -Fire SBC offers unparalleled opportunities for developers, hobbyists, and researchers to explore and experiment with RISC-V technology.

SiFive is a team of one of the pioneering engineers that helped create RISC-V instruction set architecture (ISA) and helped the ecosystem grow. The company has been an active member of the RISC-V community and contributed its guidance on various RISC-V extensions. However, according to sources close to More Than Moore, the company is reportedly downsizing its team, and layoffs are imminent. The impact of the downsizing is about 20% of the workforce, which equals around 120-130 staff. However, that is only part of the story. SiFive is reportedly also canceling its pre-designed core portfolio and shifting focus on custom-design core IP that it would sell to customers. This is in line with the slowing demand for their pre-designed offerings and the growing demand for AI-enhanced custom silicon. The company issued a statement for Moore Than Moore.

SiFive PR for Moore Than MooreAs we adjust to the rapidly changing semiconductor end markets, SiFive is realigning across all of our teams and geographies to better take advantage of the opportunities ahead, reduce operational complexities and increase our ability to respond quickly to customer product requirements. Unfortunately, as a result some positions were eliminated last week. The employees are being offered severance and outplacement assistance. SiFive continues to be excited about the momentum and long-term outlook for our business and RISC-V.

Additionally, there was another statement for More Than Moore, which you can see entirely below.

Zero ASIC, a semiconductor startup, came out of stealth today to announce early access to its one-of-a-kind ChipMaker platform, demonstrating a number of world firsts:

• 3D chiplet composability enabling billions of new silicon products
• Fully automated no-code chiplet-based chip design
• Zero install interactive RTL-based chip emulation
• Roadmap to 100X reduction in chip development costs

"Custom Application Specific Integrated Circuits (ASICs) offer 10-100X cost and energy advantage over commercial off the shelf (COTS) devices, but the enormous development cost makes ASICs non-viable for most applications," said Andreas Olofsson, CEO and founder of Zero ASIC. "To build the next wave of world changing silicon devices, we need to reduce the barrier to ASICs by orders of magnitude. Our mission at Zero ASIC is to make ordering an ASIC as easy as ordering catalog parts from an electronics distributor."

Qualcomm Technologies, Inc. announced today that they are building on their long-standing collaboration with Google by bringing a RISC-V based wearables solution for use with Wear OS by Google. This expanded framework will help pave the way for more products within the ecosystem to take advantage of custom CPUs that are low power and high performance. Leading up to this, the companies will continue to invest in Snapdragon Wear platforms as the leading smartwatch silicon provider for the Wear OS ecosystem.

"Qualcomm Technologies have been a pillar of the Wear OS ecosystem, providing high performance, low power systems for many of our OEM partners," said Bjorn Kilburn, GM of Wear OS by Google. "We are excited to extend our work with Qualcomm Technologies and bring a RISC-V wearable solution to market."
"We are excited to leverage RISC-V and expand our Snapdragon Wear platform as a leading silicon provider for Wear OS. Our Snapdragon Wear platform innovations will help the Wear OS ecosystem rapidly evolve and streamline new device launches globally," said Dino Bekis, vice president and general manager, Wearables and Mixed Signal Solutions, Qualcomm Technologies, Inc.

Tenstorrent, a company that sells AI processors and licenses AI and RISC-V IP, announced today that it selected Samsung Foundry to bring Tenstorrent's next generation of AI chiplets to market. Tenstorrent builds powerful RISC-V CPU and AI acceleration chiplets, aiming to push the boundaries of compute in multiple industries such as data center, automotive and robotics. These chiplets are designed to deliver scalable power from milliwatts to megawatts, catering to a wide range of applications from edge devices to data centers.

To ensure the highest quality and cutting-edge manufacturing capabilities for its chiplet, Tenstorrent has selected Samsung's Foundry Design Service team, known for their expertise in silicon manufacturing. The chiplets will be manufactured using Samsung's state-of-the-art SF4X process, which boasts an impressive 4 nm architecture.

During the China Chip Storage Future 2023 Storage Industry Trend Summit, Yingren Technology, widely recognized as InnoGrit outside of China, announced the initiation of mass production of its enterprise-level YR S900 PCIe 5.0 SSD controller. Marking a significant breakthrough, the YR S900 stands as China's first domestic PCIe 5.0 SSD controller. Operating on an open-source RISC-V architecture, the YR S900 is engineered to align with U.S. export restrictions, ensuring a seamless design and manufacturing process of the SSD controller. While Yingren Technology remains discreet about the specific process node to produce the YR S900, it's known that the controller embodies a versatile design, with compatibility extending to mainstream NAND from eminent manufacturers, and exhibits an impressive synergy with NAND from Yangtze Memory Technologies Corp (YMTC).

The YR S900 is a quad-channel controller, offering sequential read and write speeds peaking at 14 GB/s and 12 GB/s, respectively, and is equipped with InnoGrit's third-generation ECC engine to optimize 4K LDPC encoding and decoding. This collaboration with Kioxia's XL-Flash results in a low 4K random read latency of 10us, highlighting its potential to deliver higher data throughput, increased stability, and extended service life. The YR S900 encompasses a comprehensive feature set, including FDP, SR-IOV hardware virtualization, CMB, and a range of data encryption algorithms. While the mass production of the YR S900 underscores a monumental stride in SSD solutions within China, it remains to be seen whether adopting this new Chinese technology will enter markets beyond China.

To address customers' growing needs, Intel expanded its Intel Agilex FPGA portfolio and broadened its Programmable Solutions Group (PSG) offerings to handle the increased demand for customized workloads, including enhanced AI capabilities, and to provide lower total cost of ownership (TCO) and more complete solutions. These new products and technologies will be the focus of Intel's FPGA Technology Day (IFTD) on Sept. 18, where hardware engineers, software developers and system architects can interact with Intel and partner experts.

FPGAs play an important role in Intel's portfolio by offering flexible and customizable platform capabilities for demanding applications and workloads. Intel FPGAs solve customer challenges from cloud to edge with AI capabilities across silicon, IP and software. Intel's latest announcements illustrate how the company's increased investment in its FPGA portfolio is unfolding. So far in 2023, Intel has released 11 of 15 expected new products - more new product introductions than ever in Intel's FPGA business. As disclosed in its second quarter 2023 earnings call, Intel reported that its PSG business unit delivered 35% revenue growth year-over-year, marking the third consecutive quarter of record revenue.

Andes Technology, a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V International, today proudly announces general availability of the high-performance AndesCore AX45MPV multicore vector processor IP. The AX45MPV is the third generation of the award winning AndesCore vector processor series. Equipped with powerful RISC-V vector processing and parallel execution capability, it targets the applications with large volumes of data such as ADAS, AI inference and training, AR/VR, multimedia, robotics, and signal processing.

Andes and Meta started collaboration on datacenter AI with RISC-V vector core from early 2019. Andes later unveiled the AndesCore NX27V, marking a significant milestone as the industry's first commercial RISC-V vector processor core with the capability of generating up to 4 512-bit vector (VLEN) results per cycle, at the end of 2019. It immediately attracted the attention of worldwide SoC design teams working on AI accelerators, and has landed over a dozen datacenter AI projects. Since then, the RISC-V vector processor cores have become the choice for ML and AI chip vendors.

MIPS, a leading developer of high- performance RISC-V compute IP, has announced embedded systems industry veteran Sameer Wasson as the company's new CEO. Before joining MIPS, Wasson spent 18 years at Texas Instruments (TI), most recently as Vice President, Business Unit (BU) Manager, Processors, where he was responsible for the company's Processor businesses. In that role, Wasson re-established TI as a mainstream microprocessor (MPU) and microcontroller (MCU) supplier for high growth automotive and industrial markets, and established the company's footprint in embedded AI, software defined vehicles, and electrification.

As the new CEO of MIPS, Wasson will further accelerate the company's leadership in the High-Performance RISC-V market as it continues to expand its footprint in Automotive and Enterprise markets.