Wednesday, December 12th 2018
Intel Unveils a Clean-slate CPU Core Architecture Codenamed "Sunny Cove"
Intel today unveiled its first clean-slate CPU core micro-architecture since "Nehalem," codenamed "Sunny Cove." Over the past decade, the 9-odd generations of Core processors were based on incrementally refined descendants of "Nehalem," running all the way down to "Coffee Lake." Intel now wants a clean-slate core design, much like AMD "Zen" is a clean-slate compared to "Stars" or to a large extent even "Bulldozer." This allows Intel to introduce significant gains in IPC (single-thread performance) over the current generation. Intel's IPC growth curve over the past three micro-architectures has remained flat, and only grew single-digit percentages over the generations prior.
It's important to note here, that "Sunny Cove" is the codename for the core design. Intel's earlier codenaming was all-encompassing, covering not just cores, but also uncore, and entire dies. It's up to Intel's future chip-designers to design dies with many of these cores, a future-generation iGPU such as Gen11, and a next-generation uncore that probably integrates PCIe gen 4.0 and DDR5 memory. Intel details "Sunny Cove" as far as mentioning IPC gains, a new ISA (new instruction sets and hardware capabilities, including AVX-512), and improved scalability (ability to increase core-counts without running into latency problems).
The first products featuring "Sunny Cove" cores is slated as early as by 2019, and will be built on Intel's 10 nm DUV silicon fabrication process. Intel didn't stop at "Sunny Cove," and went on to mention two of its successors. "Willow Cove" is an incremental update, letting its designers eke out more effective IPC by improving on-die caches, transistor optimization, and the addition of new security features. In many ways, "Sunnycove" and "Willow Cove" relate to each other like AMD's "Zen" and "Zen+." The first "Willow Cove" based processors will launch in 2020, based on a refined 10 nm process node.
Lastly there's "Golden Cove," slated for 2021. Here Intel could take advantage of a newer silicon fabrication process (either an extremely refined 10 nm-derivative or even 7 nm EUV), to increase IPC (single-thread performance). In addition, Intel will improve the core's "AI performance" (probably the ability to multiply matrices), and improved host-signal processing for 5G and networking.
Intel's low-power architectures see "Tremont" succeed "Goldmont" in 2019, packing increased IPC, battery management, and network HSP. "Gracemont," slated for 2021, will improve IPC further, and improve "Vector performance," possibly heralding AVX in some form to the low-power architecture. Gracemont is succeeded by "next" mont (Intel hasn't decided a codename yet) in 2022+, with even higher IPC.
Source:
Anandtech
It's important to note here, that "Sunny Cove" is the codename for the core design. Intel's earlier codenaming was all-encompassing, covering not just cores, but also uncore, and entire dies. It's up to Intel's future chip-designers to design dies with many of these cores, a future-generation iGPU such as Gen11, and a next-generation uncore that probably integrates PCIe gen 4.0 and DDR5 memory. Intel details "Sunny Cove" as far as mentioning IPC gains, a new ISA (new instruction sets and hardware capabilities, including AVX-512), and improved scalability (ability to increase core-counts without running into latency problems).
Intel's low-power architectures see "Tremont" succeed "Goldmont" in 2019, packing increased IPC, battery management, and network HSP. "Gracemont," slated for 2021, will improve IPC further, and improve "Vector performance," possibly heralding AVX in some form to the low-power architecture. Gracemont is succeeded by "next" mont (Intel hasn't decided a codename yet) in 2022+, with even higher IPC.
57 Comments on Intel Unveils a Clean-slate CPU Core Architecture Codenamed "Sunny Cove"
Hell, prior to this, Intel even introduced 4c/8t and 4c/4t CPU to HEDT!!! lolPlease pass the dutchey to me.
4c/8t on mainstream has been around for around 8 years (2600K), and just NOW can be used by the majority. Cue Bulldozer and Zen dropping 6c+ CPUs into the mainstream BEFORE Intel who sat with 4/8 until very recently, a response to AMD's move as I said. This isn't a chicken or the egg thing unless I am missing something...
Also, the i7 920 was a HEDT CPU (on X58), NOT a mainstream CPU. We are not talking about HEDT in the first place... I purposely said MAINSTREAM to differentiate that fact.
The HEDT platform is where the HCC chips are supposed to go and HCC on that platform is the norm. AMD competed there as well with Opterons and all. AMD was the first, with BULLDOZER to bring more cores where it wasn't needed... the mainstream space. There really isn't any getting around that.
Phenom 2 had no Smt at all 4c 4t and upto 6c6t.
@EarthDog i heard that kind of bullshit in the dual core era, ie we don't need duals quads blah blah same shit different day.
So we don't need raytracing either then?, Progress in software doesn't come without platforms being out there in customer's hands already to make coding for them viable ,financially.
Or do we all Just want to play csgo for the next 40 years.
I frvkin hate RTX but I cannot knock the ideology and effort to make it happen.
Ps evey time i read "we don't needs more cores " i was ALLWAYS needing MOAR cores.
More cores adds more Alus and execution unit's.
To add ipc you need to add more Alus or execution units.
Both simple but true facts which adequately indicate Ipc has also hit a wall of sorts imho so cores wins for me.
I understand where you're coming from though and actually agree not everyone will need more, yet :D.
This is new intel they're innovative again bringing new shit like 2.5+3d chips and active interposers and mcm glued together chips it's all at the edge of what's possible and a first ;):p
Skylake-SP => Two LD/STA + One STA + One STD
Sunnycove => Two LD + Two STA + Two STD
Skylake reservation station is singular. There is one across all ports. Hence => 97 RS entries.
Sunnycove is suppose to have a clustered MEU. So, one scheduler for the Int/FP and two memory schedulers for Load/Store. One MEU for each thread.
Softmachines was bought and brought in to speed up Sunnycove's launch. So, it isn't really any surprise it re-uses the Int/FP side of Skylake-SP/Cannonlake. However, Willowcove is the actual big core planned and is supposely to receive the new Int/FP. Which by the way is suppose to be as clustered as the MEU.
Pre-2013 plans:
Haswell(Xeon) + Kittson(Itanium)
Skylake(Xeon) + Sunnycove(Itanium)
Cannonlake(Xeon) + Willowcove(Itanium)
//2014 and beyond Itanium was dropped for a faster/bigger x86 core. Sunnycove started development with Skylake, Willowcove started development with Cannonlake.
As Anandtech said;
"Frequency is often a function of the implementation and process, whereas IPC increases can come from cores being wider (more executing instructions per clock), deeper (more parallelism per clock), and smarter (better data delivery through the front end)."
I also want to remind you that this architecture was designed prior to the launch of Zen.
Also, Intel's dump to 6-core mainstream CPUs was known prior to Zen.
That does still leave some iteration of Phenom or Bulldozer as the mainstream precursor for 6c, correct?
And Bulldozer for 8 "cores".As I mentioned in my first post, the design of Ice Lake (which uses Sunny Cove) was completed by 2017-06-08.
What they've done since then is implement security mitigations and do tweaks.
Like that sunny cove is still only an ace up their greedy sleeves, they are actually far beyond that. So is Amd.
Why would You show all Your aces, if You just need to one up competition, right?
F it. I'm moving to some banana republic to play with rocks and sticks.
Look around you, everyone made the shift towards many cores designs , in desktop chips, mobile SoCs, embedded. You would also be shocked to find out that many modern CPU core designs execute many instructions concurrently anyway. If there wasn't a need for it they wouldn't have done it. You need to be extremely out of touch to believe everyone is adding more cores because the idiots didn't realize better IPC and single core performance is better.
Absolutely everything is nowadays optimized for added parallelism because that's the only way forward. You know better than multi billion dollar companies ?
Edit: side note... according to steam stats, a full 86% of users have 2c or 4c cpus. Another ~9% have 6c. One would think if the need is as high as you seem to infer (just because companies are making them isn't a reason and doesn't make it a need) more users would be on higher core count CPUs already, don't you think? I mean, hw/sw industry don't agree... which is fine, they are trying to make money first and foremost, no? If there isn't a need, create one which is what they have done over generations. We are still balls deep in an era where 4c/8t are being used by 86% of steam users, a full 95% have 6c CPUs or less. The biggest growth of CPUs in the chart.... 4c CPUs. It takes time for change. Again, 4c CPUs are now considered a minimum for most when building a PC with 4c/8t being a more optimal choice. There isn't a need for all the parallelism that you feel is prevalent now (it is the way forward, but its moving at the same turtle pace it did 10 years ago it feels).
EDIT2: Yes, I know there is more to PCs than games. Prosumers do not make up huge portion of users either. ;)