News Posts matching "10 nm"

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Lenovo Yoga Book Generation 2 Beats Apple in the Style Game

Lenovo, at Intel's Computex presser, revealed a product that could put Apple design to shame. The new Yoga Book Generation 2 is a notebook+tablet convertible, with two displays on the opposite sides of the conventional clam-shell. In the notebook mode, the bottom half converts to a keyboard, with actuators providing tactile feedback. Since the bottom half's screen is a touchscreen as much the top half, you can configure the keyboard layout and "trackpad" position any which way you want. When not typing, the bottom half becomes an extended screen of the top half. Under the hood is a "new generation" processor (very likely the 10 nm Core M3-8114Y).

An ARM to Rule Them All: ARM 76 To Challenge x86 Chips in the Laptop Space?

ARM has announced their next, high-performance computing solution with their A76 design, which brings another large performance increase to the fledgling architecture. having been touted for some time as a true contender to the aging x86 architecture, ARM has had a way of extracting impressive performance increases with each iteration of its computing designs, in the order of 20% do 40% performance increases in an almost annual basis. Compare that to the poster-child of x86 computing, Intel, and its passivity-fueled 5 to 10% yearly performance increases, and the projections aren't that hard to grasp: at some point in time, ARM cores will surpass x86 in performance - at least on the mobility space.

The new ARM A76 design, to be manufactured on the 7 nm process, brings about a 35% increase in performance compared to last years' A75. This comes with an added 40% power efficiency (partly from the 10 nm to 7 nm transition, the rest from architecture efficiency and performance improvements), despite the increase to maximum 3.0 GHz clocks. With the added performance, ARM is saying the new A76 will deliver 4x the Machine Learning performance of its previous A75 design.

Samsung Announces 10 nm-Class DDR4 SO-DIMMs for Gaming Notebooks

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, today announced that it has started mass producing the industry's first 32-gigabyte (GB) double data rate 4 (DDR4) memory for gaming laptops in the widely used format of small outline dual in-line memory modules (SoDIMMs). The new SoDIMMs are based on 10-nanometer (nm)-class process technology that will allow users to enjoy enriched PC-grade computer games on the go, with significantly more capacity, higher speeds and lower energy consumption.

Using the new memory solution, PC manufacturers can build faster top-of-the-line gaming-oriented laptops with longer battery life at capacities exceeding conventional mobile workstations, while maintaining existing PC configurations. "Samsung's 32GB DDR4 DRAM modules will deliver gaming experiences on laptops more powerful and immersive than ever before," said Sewon Chun, senior vice president of memory marketing at Samsung Electronics. "We will continue to provide the most advanced DRAM portfolios with enhanced speed and capacity for all key market segments including premium laptops and desktops."

Possible Intel 8-core LGA115x Processor Surfaces on SANDRA Database

That Intel bringing 8 cores to the mainstream-desktop (MSDT) platform is more than a rumor now, as a curious-looking SiSoft SANDRA database entry suggests. An anonymous source submitted benchmark results of a processor with 8 cores, 16 threads, 256 KB of L2 cache per core, and 16 MB of L3 cache; clocked at 2.60 GHz (prototypes and engineering-samples are usually clocked low). This can't be i7-5960X or the i7-6900K, because the HEDT chips pack 20 MB of L3 cache. The more recent i7-7820X packs 11 MB of L3 cache, with 1 MB per core of L2 cache. It's conceivable that an MSDT chip could retain the cache hierarchy of the current MSDT processors from Intel, with 2 MB L3 cache slices per core, adding up to 12 MB on the i7-8700, for example, explaining the large 16 MB L3 cache on this chip.

The SANDRA numbers suggest similar IPC to the "Coffee Lake" architecture, while a proportionate increase in performance to the increased core-count. The chip scored 96 points with 237.03 GOPS score; 330.64 GIPS Dhrystone integer, 194.46 GFLOPS Whetstone single-precision floating-point; and 148.47 GFLOPS Whetstone double-precision; and 91.45 GOPS/GHz clocks/performance. Intel is rumored to launch an 8-core/16-thread LGA115x processor, possibly paired with its upcoming Z390 Express chipset, and possibly based on its new 10 nm silicon fabrication process; sometime either in 2H-2018 or Q1-2019.

Intel Core M3 8114Y "Cannon Lake-Y" Processor Surfaces in 3DMark

The Intel Core i3-8121U was the first Cannon Lake processor to be revealed to the public. Today, we got word of the existence of another 10 nm chip. The Intel Core M3 8114Y, as its name implies, belongs to the low-powered Cannon Lake-Y family. It's a dual-core processor with four threads that runs at a base clock of 1.5 GHz. Although there was no mention of the processor's boost clocks, the Core M3 8114Y is expected to boost to 2.2 GHz. Like its predecessor, the chip should have a 4.5 W TDP. The 3DMark results also revealed that this model in particular supports LPDDR4 memory. Unlike the Core i3-8121U which has its iGPU disabled, the Core M3 8114Y comes with an Intel UHD Graphics iGPU.

Intel "Cannon Lake" Confirmed to Feature AVX-512 Instruction-Set

Intel updated the ARK information page for its stealthily launched 10 nm production chip, the Core i3-8121U "Cannon Lake," to confirm that the chip supports the new AVX-512 instruction-set. This is the first "mainstream" client-segment processor by the company to feature the extremely advanced instruction-set that, if implemented properly on the software side, can double performance/Watt compared to tasks that can take advantage of AVX2.

The instruction-set made its debut with the Xeon Phi "Knights Landing" HPC processor, and made its client-segment debut with the Core X "Skylake X" HEDT processors. It remains to be seen if the implementation of AVX-512 on "Cannon Lake" is complete, or if some instructions found on HPC processors such as the Xeon Phi are omitted due to irrelevance to the client platform.

A Push for the Higher Margin: Intel Reportedly Discontinues Production of Its H310 Chipset

A report straight out of DigiTimes, citing industry sources, says that Intel has discontinued production of its H310 chipset. The decision has apparently stemmed from lower than expected production capacity for chipsets on the 14 nm process. When that happens, production focus must shift to a specific part: in this case, Intel obviously went with the option with the lower opportunity cost, and increased production of the Z370 chipset: the one with the increased feature-set, and, most likely than not, higher margins.

After a single month of tight supply for the H310 chipset, motherboard makers are now forced to use Intel's B360 chipset in their more cost-conscious options as well - a part which carries higher cost, and thus precludes manufacturers from hitting all the price points they usually would with a fully vertical Intel chipset lineup. Speculation has emerged claiming Intel suspended the supply of H310 because they have chosen to conduct a manufacturing process change from the tight-supply 14 nm (used across almost all of Intel's production stack, both consumer and enterprise) to a 22 nm fabrication technology. Further speculation places this constrained 14 nm supply as existent because of the delay in advancing to 10 nm, a process that Intel expected to be producing in volume by now (and since a while back, to be fair).

Intel Reports First Quarter 2018 Financial Results

Intel Corporation today reported first-quarter 2018 financial results. "Coming off a record 2017, 2018 is off to a strong start. Our PC business continued to execute well and our data-centric businesses grew 25 percent, accounting for nearly half of first-quarter revenue," said Brian Krzanich, Intel CEO. "The strength of Intel's business underscores my confidence in our strategy and the unrelenting demand for compute performance fueled by the growth of data."

"Compared to the first-quarter expectations we set in January, revenue was higher, operating margins were stronger and EPS was better," said Bob Swan, Intel CFO. "Our data-centric strategy is accelerating Intel's transformation, and we're raising our earnings and cash flow expectations for the year." In the first quarter, the company generated approximately $6.3 billion in cash from operations, paid dividends of $1.4 billion and used $1.9 billion to repurchase 41 million shares of stock.

Intel's Next Atom Core, Tremont, Revealed - Likely to Be Fabbed on the 10 nm Process

Intel, via its internal documentation that is, routinely, the source of new information on unreleased products, has revealed their next low-power architecture. Codenamed Tremont, the new architecture is expected to be developed on the company's 10 nm process (not unlike Ice Lake) and bring some performance improvements to the company's options for the embedded market.

Tremont will thus replace Intel's Goldmont Plus, which is still being manufactured on the company's 14 nm process (it hasn't been side-graded to the company's 14 nm + or ++ processes, due to these being less suited for denser chip designs). The new architecture will likely receive some specific performance improvements that mirror some of Intel's Core architecture's improvements, alongside support for new instruction sets - CLWB, GFNI (SSE-based), ENCLV, Split Lock Detection instruction set extensions are all extensions that will also be introduced in the company's Ice Lake cores, which increases the likelihood of the same process. Other functions introduced specifically for Tremont include CLDEMOTE, direct store, and user wait instructions.

Intel Could Develop its own big.LITTLE x86 Adaptation

big.LITTLE is an innovation by ARM, which seeks to minimize power-draw on mobile devices. It is a sort of heterogeneous multi-core CPU design, in which a few "big" high-performance CPU cores work alongside a few extremely low-power "little" CPU cores. The idea here is that the low-power cores consume much lesser power at max load, than the high-performance cores at their minimum power-state, so the high-performance cores can be power-gated when the system doesn't need them (i.e. most of the time).

Intel finds itself with two distinct x86 implementations at any given time. It has low-power CPU micro-architectures such as "Silvermont," "Goldmont," and "Goldmont Plus," etc., implemented on low-power product lines such as the Pentium Silver series; and it has high-performance micro-architectures, such as "Haswell," "Skylake," and "Coffee Lake." The company wants to take a swing at its own heterogeneous multi-core CPU, according to tech stock analyst Ashraf Eassa, with the Motley Fool.

AMD "Vega 20" Optical-Shrunk GPU Surfaces in Linux Patches

AMD "Vega 20" is rumored to be an optical shrink of the current "Vega 10" GPU die to a newer process, either 12 nm, or 10 nm, or perhaps even 7 nm. Six new device IDs that point to "Vega 20" based products, surfaced on AMD's GPU drivers source code, with its latest commit made as recently as on 28th March. AMD "Vega 10" is a multi-chip module of a 14 nm GPU die, and two "10 nm-class" HBM2 memory stacks, sitting on a silicon interposer that facilitates high-density wiring between the three. In an effort to increase clock speeds, efficiency, or both, AMD could optically shrink the GPU die to a smaller silicon fabrication process, and carve out a new product line based on the resulting chip.

China's Tsinghua Unigroup to Manufacture 3D NAND Flash for Intel

In a bid to ensure sufficient supply of NAND flash memory to meet the growing demands of not just PC, but also smartphone markets, China's Tsinghua Unigroup and Intel are in talks to license-manufacture 64-layer 3D NAND flash, based on existing IMFlash Technologies designs. IMFlash is a joint-venture between Intel and Micron Technology. Tsinghua Unigroup is one of the biggest beneficiaries of the Chinese Government's ambitious plan to invest RMB 1 trillion (USD $158 billion) over the next five years, to increase China's semiconductor self-sufficiency to 70 percent, by 2025.

The move will significantly increase supply of NAND flash memory, and is seen as a market threat to Korean NAND flash giants Samsung and SK Hynix, and Japanese Toshiba. IMFlash Technology released its first 64-layer 3D NAND flash to the market in 2017, and is currently developing a 96-layer 3D NAND flash chip, which, along with newer 10 nm-class silicon fabrication process, could double densities over the current 64-layer chips.

Intel Plans $5 billion Investment in Israel Plant for Expanded 10 nm Production

Israeli Economy Minister Eli Cohen today revealed that after talks with Intel, the company shared plans for a $5 billion investment in its Kiryat Gat plant, located in southern Israel. The Kiryat Gat plant currently features tools and manufacturing facilities that allow only 22 nm chips to be produced - definitely not cutting edge, but still somewhat relevant in the semiconductor market for simpler technologies. Intel's investment would bring this plant's capabilities to 10 nm manufacturing levels. The minister further stated that Intel will begin its investment this year, and was looking towards a full 2020 payoff with increased manufacturing capabilities. Naturally, with investment comes tax opportunities and government incentives, and Intel is expected to receive a 10% grant from the Israeli government to help it in this investments' funding.

Intel "Ice Lake-U" Gen 11 iGPU Features 48 Execution Units

Intel's next generation "Ice Lake" processor could integrate a significantly faster integrated graphics solution (iGPU), if a SiSoft SANDRA online database entry is to be believed. A prototype "Ice Lake" chip was benchmarked, with its iGPU being described by the database as "Intel UHD Graphics" based on the company's Gen 11 graphics architecture, which succeeds the current Gen 9.5 architecture implemented on "Coffee Lake" and "Kaby Lake." This iGPU is endowed with 48 execution units (EUs), which work out to 384 unified shaders; against 24 EUs and 192 shaders on Intel UHD 620. SANDRA also describes the iGPU as being able to share up to 6 GB of memory from the system memory; and featuring 768 KB of dedicated cache. Its reference clock is 600 MHz, double that of the UHD 620, although its boost clock remains a mystery. "Ice Lake" is being built on Intel's new 10 nm+ silicon fabrication process, so it's understandable for the company to significantly enlarge its iGPU.

Samsung 860 EVO SSD Makes an Appearance

Hot on the heels of Samsung updating its website with its next performance-segment SSD 860 Pro series, with its range-topping 4 TB variant, a similar pre-launch website update revealed the company's next mainstream SATA SSD, the 860 EVO. The drive will be available in three form-factors, 7 mm-thick 2.5-inch, M.2-2280, and mSATA; all with SATA 6 Gbps interface. The 2.5-inch version comes in 250 GB, 500 GB, 1 TB, 2 TB, and 4 TB variants; while the M.2-2280 version comes in just 500 GB, 1 TB, and 2 TB variants; and the mSATA version in 250 GB, 500 GB, and 1 TB variants. The drives combine Samsung's latest generation 3D VNAND flash memory built in the 10 nm-class sliicon fabrication process, with an updated controller and refined firmware.

The 860 EVO offers sequential transfer rates of up to 550 MB/s, with up to 520 MB/s sequential writes, up to 97,000 IOPS 4K random reads, and up to 88,000 IOPS 4K random writes. The new-generation flash is rated for "8 times higher" endurance than the 850 EVO series; with up to 2,400 TBW. Samsung is reinforcing its faith in the drive by backing it with 5-year warranties. The company is introducing the new TurboWrite feature, which is a user-configurable SLC cache. You can set anywhere between 12 GB to 72 GB of the NAND flash to function as SLC, so the controller can juggle hot data in and out of it, for improved performance, using the Samsung Magician software.

HWiNFO Adds Support for Intel Ice Lake, Whiskey Lake, AMD 400-Series Chipset

HWiNFO v. 5.7 has brought with it a smattering of improvements and additions, as is usually the case. These are worthier of a news piece than most, however, since we're looking at quite a number of interesting developments. For one, preliminary support has been added for Intel's Whiskey Lake, an upcoming mobile design that succeed's Intel's Kaby Lake products, and should bring the fight to AMD's Ryzen Mobile offerings. Furthermore, and still on the Intel camp, support for the upcoming 10 nm Ice Lake has also been added. Íf you'll remember, Ice Lake is expected to be Intel's first foray into the 10 nm+ process in the mobile camp (given away by the U/Y product codes), after numerous delays that made the company stick with its 14 nm process through three iterations and in-process improvements. These are not the only Intel developments, however; the team behind HWiNFO has also added a new feature that reveals your Intel CPU's Turbo Boost multipliers, which the company has since removed form their ARK pages and processor specifications - an issue that generated rivers of ink.

Stepping away from the blue giant's camp, there's added support for AMD's next revision of their Ryzen processors (Pinnacle Ridge, on a 12 nm process). There's also mention of upcoming support for AMD's 400-series chipsets, which should improve platform features of the AM4 socket. This addition comes after we've seen its first appearance in the PCI-SIG Integrators List.

Samsung Now Mass Producing Industry's First 2nd-Generation 10nm Class DRAM

Samsung Electronics Co., Ltd., the world leader in advanced memory technology, announced today that it has begun mass producing the industry's first 2nd-generation of 10-nanometer class (1y-nm), 8-gigabit (Gb) DDR4 DRAM. For use in a wide range of next-generation computing systems, the new 8 Gb DDR4 features the highest performance and energy efficiency for an 8 Gb DRAM chip, as well as the smallest dimensions.

"By developing innovative technologies in DRAM circuit design and process, we have broken through what has been a major barrier for DRAM scalability," said Gyoyoung Jin, president of Memory Business at Samsung Electronics. "Through a rapid ramp-up of the 2nd-generation 10 nm-class DRAM, we will expand our overall 10 nm-class DRAM production more aggressively, in order to accommodate strong market demand and continue to strengthen our business competitiveness."

Intel 10 nm CPUs to See Very Limited Initial Launch in 2017

UPDATE: Some slides have surfaced today on Reddit that actually place Intel's updated 10 nm roadmap as starting initial risk production in 2Q 2018. The same leaks also point towards a yearly advancement in process technology (akin to Intel's current 14 nm+ and 14 nm++ production processes), with 10 nm+ risk production on 1Q 2019 and 10 nm++ on 1Q 2020. This roadmap, however, is relative to Intel's Custom Foundry partners; as such, this doesn't go directly against Intel CEO's Brian Kzarnich remarks on the latest investor call, since he was likely talking about the 10 nm ramp-up on Intel's own products.

Intel CEO Brian Krzanich has come out to say that the company's first 10 nm CPUs based on the "Cannon Lake" micro-architecture will see the light of day before this year's end. Intel has been having a slew of ramp-up delays with its 10 nm products, which prompted a slippage from an expected 2016, full-scale launch (whose ship has sailed, clearly) towards a timed, product-tier based strategy. Intel opted to first introduce 10 nm technology to FPGA accelerators, which due to their redundancy, would suffer less from yield issues.

Intel's First 10 nm Chips to the Market are 64-layer 3D NAND

Non-volatile memory often has the first pick of a new silicon fabrication process, as it is a low-risk development. A NAND flash chip is essentially a sea of transistors, with a fraction of R&D cost of something as specialized as a CPU die. It should come as no surprise, then, that the first chips to be built on Intel's swanky new 10 nanometer fabs will be a 64-layer 3D NAND flash memory, the first of its kind for data center applications.

With its 10 nm process, Intel is introducing FinFET Hyper Scaling, Intel will increase transistor densities by 2.7 times over the kind of densities one would traditionally expect from 10 nm. This lets the company scale up NAND flash storage densities by just that much more. The first 10 nm 64-layer 3D NAND flash chips will have high data densities, while at the same time, Intel will be able to push low volumes, characteristic of a new process. This explains why the first SSDs built with these chips are targeted at data-centers, so fairly expensive, high-capacity SSDs can be pushed to customers that can afford them.

Intel's 10 nm Technology Bound for FPGAs First; Wafer Showcased

Intel is undoubtedly at the forefront of silicon processing technology these days, and has been for a long time. Being a fully integrated company from the bottom up, through the design and actual production of its silicon semiconductors, really does have a way of either paying of tremendously (as has been the case with Intel), or not at all (as was the case with AMD). That fabrication processes' nm ratings don't mean much in thhe industry right now has been the case for a while now; different companies use different calculations towards achieving a 22 nm or 14 nm claim, with some components in the same nm process having almost double the size of the same components in a competitor's equivalent. Intel has always been one of the more adamant defenders of an industry-wide categorization, both to avoid confusion and - naturally - put into perspective their process leadership.

Intel Officially Reveals What's Coming After Coffee Lake: The 10 nm Ice Lake

A pretty underwhelming post on Intel's official page has pulled the curtains of the company's architecture name post their 8th generation processors. Actually, it's a little more puzzling than that, since Intel is actually detailing the codename of an architecture that's supposed to come right after their 8th generation - read, Coffee Lake - processors. Keep in mind that Coffee Lake, whilst being supposed to bring a reorganization of Intel's product stack in response to AMD's Ryzen success, will still be in the 14 nm++ process - the third such architecture in the same process, after Skylake (14 nm) and Kaby Lake (14 nm+) before it. Cannon Lake, however, is supposed to be the company's first tick into the 10 nm process.

Intel has moved over from their famed tick-tock (where tick is a process shrink and tock is a new architecture on the same process) cadence, and are now telling customers to expect at least three "tocks" per process. It's expected that Intel will launch mobile processors on the 10 nm process before any desktop parts are launched on the same process; this could stem from the fact that mobile parts are typically lower-power, smaller-sized dies, which are easier and cheaper to produce out of a still maturing 10 nm process, which usually implies lower than ideal yields.

Intel Coffee Lake Six-core Processor Rears its Head on SiSoftware Sandra

After the absence of some further details on Intel's upcoming Coffee Lake mainstream CPU architecture (which is understandable, really, considering how the X299 platform and accompanying processors are all the rage these days), some new details have emerged. Intel's Coffee Lake architecture will still be manufactured on the company's 14 nm process, but is supposedly the last redoubt of the process, with Intel advancing to a 10 nm design with subsequent Cannon Lake.

The part in question is a six-core processor, which appears identified as a Genuine Intel CPU 0000 (so, an engineering sample.) SiSoft Sandra identifies the processor as a Kaby Lake-S part, which is probably because Coffee Lake processors aren't yet supported. The details show us a 3.1 GHz base, and a 4.2 GHz boost clock, with a 256 Kb L2 cache per core and a total of 12 MB L3 (so, 2 MB per core, which is in-line with current Kaby Lake offerings.) The 6-core "Coffee Lake" silicon will be built on a highly-refined 14 nm node by Intel, with a die-size of 149 mm². Quad-core parts won't be carved out of this silicon by disabling two cores, but rather be built on a smaller 126 mm² die.

Intel Announces 9th Gen Core "Cannon Lake" On Track, "Ice Lake" Taped Out

Intel announced that its first CPU micro-architecture built on its upcoming 10 nanometer silicon fab process, the 9th generation Core "Cannon Lake," is on track. In a tweet on the official company account, Intel also announced that its second micro-architecture on the new 10 nm process, codenamed "Ice Lake," is taped out.

In the wake of a competitive CPU lineup by AMD, Intel is frantically upgrading its product lineup, beginning with the new "Basin Falls" HEDT platform early-Summer 2017, followed by its 14 nm "Coffee Lake" 8th generation Core series late-Summer. "Coffee Lake" sees the first six-core SKUs to Intel's mainstream desktop lineup, which has until now, been restricted to dual-core and quad-core parts.

AMD Doesn't Regret Spinning off GlobalFoundries

AMD co-founder Jerry Sanders, in 2009 was famously quoted as stating that "real men have fabs," a jibe probably targeted at the budding fab-less CPU designers of the time. Years later, AMD spun-off its silicon fabrication business, which with a substantial investment of the Abu Dhabi government through its state-owned Advanced Technology Investment Company (ATIC), became GlobalFoundries (or GloFo in some vernacular). This company built strategic partnerships with the right players in the industry, acquisitions such as IBM's fabs, and is now at the forefront of sub-10 nm fab development. It remained one of AMD's biggest foundry partners besides TSMC and Samsung, and is manufacturing its AMD processors at a brand new facility in Upstate New York, USA.

AMD, on the other hand, doesn't regret spinning off GloFo. Speaking at Merrill Lynch Global Technology and Investment Conference, CTO Mark Papermaster said, that going fab-less has helped AMD focus on chip-design without worrying about manufacturing. Production is no longer a bottleneck for AMD, as it can now put out manufacturing contracts to a wider variety of foundry partners. Its chip-designers aren't limited by the constraints of an in-house fab, and can instead ask external fabs to optimize their nodes for their chip-designs, Papermaster said. 14 nm FinFET has added a level of standardization to the foundry industry.

Samsung Announces Comprehensive Process Roadmap Down to 4 nm

Samsung stands as a technology giant in the industry, with tendrils stretching out towards almost every conceivable area of consumer, prosumer, and professional markets. It is also one of the companies which can actually bring up the fight to Intel when it comes to semiconductor manufacturing, with some analysts predicting the South Korean will dethrone Intel as the top chipmaker in Q2 of this year. Samsung scales from hyper-scale data centers to the internet-of-things, and is set to lead the industry with 8nm, 7nm, 6nm, 5nm, 4nm and 18nm FD-SOI in its newest process technology roadmap. The new Samsung roadmap shows how committed the company is (and the industry with it) towards enabling the highest performance possible from the depleting potential of the silicon medium. The 4 nm "post FinFET" structure process is set to be in risk production by 2020.

This announcement also marks Samsung's reiteration on the usage of EUV (Extreme Ultra Violet) tech towards wafer manufacturing, a technology that has long been hailed as the savior of denser processes, but has been ultimately pushed out of market adoption due to its complexity. Kelvin Low, senior director of foundry marketing at Samsung, said that the "magic number" for productivity (as in, with a sustainable investment/return ratio) with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable.
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