SK hynix reported its latest Q3 2026 quarterly results with a record $78.129 billion in net revenue. However, the company also shared a market outlook, highlighting its long-term supply agreements and plans for expansion with new fab capacity and facilities under construction. For the consumer market, the outlook is grim as SK hynix expects memory demand to continue outpacing supply through 2030. The main supply constraint is the complexity of leading-edge semiconductor nodes and the lengthy lead times for fab construction, which take years to translate into regular mass production volumes.

Despite sustained demand, pricing is also on an upward trajectory, with the average selling price of memory modules in Q3 increasing by over 20% compared to Q2. This is concerning, as it suggests that the prices of consumer electronics devices might jump by more than 20% once memory inventory is depleted. Although SK hynix expects a decrease in PC and smartphone shipments, this will be offset by a strong rollout of AI data centers. About 14 major customers, including most hyperscalers, have signed 5-year long-term agreements, which will account for over 50% of total capacity sold for 2027 and 2028.

Chinese memory giant CXMT is reportedly facing difficulties with HBM3 production, according to South Korean media. Late last month, it was revealed that CXMT had begun risk production of HBM3E memory, lagging two generations behind Samsung, SK hynix, and Micron, who are already progressing with HBM4E sampling. At that time, it was known that the company was conducting HBM3E risk production in limited runs, but details were scarce. However, today we learn that three out of four HBM3E stacks are defective, indicating that CXMT currently operates at a 25% yield. Stacking DRAM is a complex task, as the technology required is much more intricate than planar DRAM manufacturing, an area where CXMT reportedly excels.

The low yields are reportedly due to the immaturity of the through-silicon via (TSV) technology that CXMT employs. In front-end manufacturing, CXMT achieves around 30% yields, while back-end processing yields about 70% on top of the original 30%. For instance, Samsung uses about 5,000 TSVs per layer on HBM2, and SK hynix uses more than 8,000 TSVs per layer on its HBM3. However, data suggests that CXMT is attempting to achieve HBM3E with only 3,000 TSVs per layer and is trying to pack 8 layers in the regular 8-Hi HBM3E configuration. Given these challenges, the company is unlikely to transition to a higher-capacity 12-Hi HBM in the near term as it addresses engineering challenges.

SK hynix is shifting much of its capacity to the latest 1c DRAM node, according to recent reports. The South Korean giant is transitioning the bulk of its memory production between nodes, and as DRAM technology advances, the company is moving its production to more advanced 10 nm-class nodes. For SK hynix, the sixth-generation 10 nm class 1c DRAM node accounted for 10% of production in Q1 2026, with an increase to about 13% in Q2. In the current third quarter, the company is expected to manufacture 24% of its DRAM on 1c, while Q4 will see more than a third (34%) produced on that node. By Q1 2027, the 1c node will account for around 35%, making the fifth-generation 10 nm-class 1b node at 33%, officially SK hynix's most dominant node.

As a reminder, DRAM nodes are not the same as conventional logic nodes. DRAM manufacturers use variations of 10 nm and scale them with more EUV layers or advanced features. For SK hynix, the currently dominant 1b node is around 12-13 nm in actual design and involves about 4 layers of EUV patterning, while the most advanced 1c node shrinks to 11-12 nm with 5-6 layers of EUV. SK hynix will use the 1c node to manufacture HBM4E, LPDDR6, and DDR5 memory. For the older 1b node, SK hynix produces DDR5, LPDDR5X, HBM3E, and HBM4.

Intel Foundry might win the contract to manufacture base dies for HBM4E memory from SK hynix, according to the South Korean Herald. Reportedly, SK hynix is considering diversifying its base die supplier from solely TSMC to a dual sourcing strategy involving both TSMC and Intel, with Intel Foundry potentially securing a significant portion of the contract. As readers may recall, HBM4E memory allows for the implementation of a base die with custom logic, with DRAM dies stacked on top. Until now, SK hynix has only considered TSMC for this application, but now Intel is also being considered.

For instance, customers could implement custom logic like memory controllers and PHYs directly on the HBM4E base die, significantly reducing the area occupied by these components on the main compute chiplet. SK hynix would send the design to Intel, which would then provide these base dies to SK hynix. The South Korean memory giant would subsequently stack DRAM on top. This approach would free up space on the main compute tile in any AI accelerator for more processing units, reduce latency, and significantly improve performance. However, the question remains as to which Intel node would be used. Up until HBM3E, SK hynix used its own nodes to manufacture base dies. However, as those are 10 nm class nodes, customers are now requiring something more advanced.

Chinese memory giant CXMT has reportedly achieved a significant milestone in DDR5 production, with manufacturing yields now comfortably above 90%. This is comparable to what major manufacturers like Samsung, SK hynix, and Micron are achieving. According to reports, CXMT uses a 17 nm node for DDR5 chip production and has reached a 90% yield for these chips. This is only 2-3% lower than Samsung's yield on its 10 nm class node for DDR5 production, indicating that CXMT's production quality is matching that of the world's largest memory maker. This is a remarkable achievement for a company that excels in cleanroom construction time, taking only 12 months to build its fab's cleanroom compared to the two years others require. As the company plans to end the year with 350,000 DRAM wafers per month, high yields mean there is little waste or leftover.

Chinese MyDrivers also notes that PC OEMs have mixed reactions to adopting CXMT DRAM in their products. For instance, Dell has completely banned the use of CXMT in its machines, while HP only allows CXMT DRAM in its Chinese PCs. Major Taiwanese brands such as ASUS and Acer have increased adoption in some models, as they have more flexibility in supply chain procurement. However, both companies use CXMT memory for PCs sold in mainland China and some emerging markets, meaning the West is still far from receiving PCs with CXMT memory modules. PC OEMs are also cautious about procuring CXMT memory due to concerns about disrupting their relationships with the big three memory makers.

Nanya Technology Board of Directors announced on August 5 that the company has launched its largest investment program, committing up to NT$346.6 billion (around $10.7 billion) to its Fab5A facility through 2026-2029. The project covers 10 nm-class processes from 1b through 1e nodes and introduces EUV lithography. Nanya has also increased its 2026 capital expenditures budget by 34% to NT$69.7 billion (around $2.16 billion). The extra NT$17.7 billion is going toward advance payments for equipment to keep Fab5A on schedule. The production roadmap has wafer starts being produced in the second half of 2027, reaching 30,000 wafers per month in 2028 and 35,900 in 2029. The maximum planned capacity is around 45,000 wafers monthly. The 1c pilot production has already begun, while the 1d node is under development and expected to enter pilot production soon. Nanya Fab5A investment, when completed, is estimated at roughly $16 billion, deployed in phases based on market demand.

Commercially, Nanya is having a strong run. July revenue hit NT$43.87 billion (around $1.3 billion), up 49.3% month over month and 719.6% year over year, driven by continued DRAM price increases, particularly sharp gains in DDR4 contract prices. Remember that just a year ago DDR4 module prices overtook DDR5 for the first time, with Nanya among the biggest beneficiaries. Its customers include giants like NVIDIA, Google, Microsoft, Intel, AMD, and Qualcomm, with the future looking great for the Taiwanese company. Its long-term agreements reportedly now cover about 50% of production capacity, with short-term contracts gradually converted into long-term agreements.

SK hynix is preparing for the mass production of its next-generation LPDDR6 memory, according to the South Korean outlet Herald. While this information isn't surprising, the timeline is now set for the second half of 2026, which began in July. Earlier rumors suggested mass production would occur in the first half of the year, as testing and trial production were completed in March. Previously, SK hynix announced that its LPDDR6 memory modules would feature a 16 Gb capacity on the sixth-generation 10 nm node, known as 1c. Although the exact speed of LPDDR6 is not yet known, it was previously reported that SK hynix is preparing modules capable of running at speeds up to 14.4 Gbps, offering a significant throughput boost over the previous-generation LPDDR5X memory. The company claims a 33% improvement over LPDDR5X, which topped out at 10.7 Gbps, aligning with the 14.4 Gbps figure for LPDDR6.

LPDDR6 will bring numerous improvements, particularly in density, power efficiency, and speed. SK hynix is also expecting significant power efficiency optimizations exceeding 20% thanks to the new technologies enabling LPDDR6 to operate. This generation of low-power DDR memory uses a sub-channel structure that allows the memory channels to operate selectively, processing only the necessary data paths. This means not all channels need to be engaged when they are not required. Additionally, LPDDR6 incorporates Dynamic Voltage and Frequency Scaling (DVFS), which optimizes power consumption and performance by dynamically adjusting the voltage and frequency depending on the scenario.

According to sources close to The Information, a Chinese company Shanghai Yuliangsheng Technology has reportedly begun limited production of immersion DUV lithography machines. This Shanghai-based company aims to produce five systems for delivery this year, with an estimated production of about 20 immersion DUV machines by 2027. While this may not seem like a large number, it represents a significant effort in developing homegrown DUV machine production, reducing reliance on third-party suppliers like ASML. The Shanghai company plans initial deliveries to SMIC, CXMT, and Hua Hong, which will integrate these machines into their production processes.

For those unfamiliar, immersion deep ultraviolet (DUV) machines use an argon-fluoride (ArF) excimer laser to produce DUV light at a 193 nm wavelength. This light travels through a layer of ultra-purified water placed above the final lens, which imprints circuit designs onto a wafer. Although this may sound straightforward, immersion DUV lithography tools are highly complex machines that ASML has been mass-producing for years. By comparison, ASML shipped 131 immersion DUV machines last year, showing the smaller scale of the Chinese production. Additionally, Chinese immersion DUV also imports some key components from Japan, while most are being sourced from China.

The Chinese DRAM market has just gained another player with POWEV entering the DDR5 market. POWEV is a sub-brand of the Chinese company Jiahe Jinwei, which announced its entry into the DDR5 market almost half a decade ago but is delivering now when it is needed most. POWEV has introduced DDR5 DRAM in form factors like UDIMM, SODIMM, and RDIMM, capable of up to 64 GB capacity and available in either 4,800 MT/s or 5,600 MT/s speeds. At these speeds, modules have different latencies, so it is best to refer to the specification table below. Firstly, POWEV separates its DDR5 products into "pure domestic" memory modules and industrial memory modules. This likely refers to some modules being for PC DIY and OEM applications, while others are for servers and industrial applications.

Both categories come with non-ECC unbuffered memory modules, while RDIMMs carry registered ECC on their own DIMMs. Every module operates at a voltage of 1.2 V, with a specific pin count depending on the form factor. Interestingly, it is unclear what technology POWEV uses to manufacture these DDR5 modules and create these DIMMs, as the underlying technology is undefined. South Korean memory makers such as SK hynix and Samsung usually reveal which iteration of their 10 nm manufacturing technology is used for chip manufacturing, but that is not the case here. Jiahe Jinwei has entered mass production of DDR5 memory, but no underlying technology has been disclosed. For many, this doesn't matter as long as the performance meets JEDEC's DDR5 specifications.

Yesterday, TSMC unveiled its latest A13 node preview at the North America Technology Symposium, highlighting the company's ongoing developments. However, the most significant news isn't about a new node but the technology behind it. TSMC announced it would rely on older ASML Low-NA EUV tools instead of the more expensive High-NA EUV scanners. With the High-NA EUV scanner priced at about €350 million ($410 million), the capital expenditure required to equip a modern facility is substantial. TSMC claims it can maintain a competitive advantage using the existing Low-NA EUV technology, which costs roughly half as much per machine. Kevin Zhang, TSMC's deputy Co-COO and SVP, noted to Reuters, "This is where I think our R&D has done exceptionally well in terms of leveraging existing EUV technology while setting an aggressive technology scaling roadmap. This is definitely a strength."

TSMC's use of Low-NA EUV lithography involves a technique called multi-patterning, where the EUV machine takes multiple passes to etch a design on a single layer. By performing two Low-NA etching runs, TSMC can achieve benefits similar to High-NA exposure, effectively reducing the need for new tools. However, there are limitations to the Low-NA multi-patterning technique, which will be addressed later by introducing High-NA systems, but only for nodes at 1 nm and below. For now, and for recent nodes, TSMC sees a way to maximize performance from the existing Low-NA systems at a much lower capital expenditure than would be required for High-NA systems.

Intel has quietly rolled out a new mobile CPU in the Raptor Lake lineup, the Core i7-13645HX. The chip is built with Intel's 10 nm process and splits its 14 cores across six Performance cores and eight Efficient cores, just like the Core i7-13650HX. That means both share the same 20-thread count, 24 MB of Smart Cache, max turbo clock at 4.9 GHz, and power specs: 55 W base, 157 W peak. However, there are some differences. The i7-13645HX supports DDR5-5600, up from 4800 on its older sibling. With that comes also an increase in memory bandwidth to 89.6 GB/s, up from 76.8 GB/s. It also sports a more capable Intel UHD Graphics P730 with 32 execution units versus just 16 on the i7-13650HX. The older part still has a slight edge in efficiency: its E-cores can boost to 3.6 GHz, while this one tops out at 3.5 GHz. But for users who need faster memory and better integrated graphics, especially those running light gaming or video workloads, the new chip might be the better choice.

Compared to the i7-13700HX, which has eight P-cores, a higher boost clock (5.0 GHz), 30 MB cache, and slightly more power headroom, this one feels like something in between, less raw performance than the top-tier HX model but with better memory support. Intel rebranded Raptor Lake as Core 200 series in late 2024, positioning it for higher-end laptops. The i7-13645HX appears to be part of that push: a refined option for systems targeting mainstream performance without stepping up to the full HX stack. No official pricing yet, as this is likely to show up in select gaming and creator machines over the next few months. Remember that just this Tuesday, Intel rolled out its Core Ultra 200HX Plus mobile processors, including the Core Ultra 9 290HX Plus and Core Ultra 7 270HX Plus. These processors add new features and architectural refinements, including support for the new Intel Binary Optimization Tool that can improve native performance in select games.

SK hynix has successfully developed new LPDDR6 memory modules with a 16 Gb capacity on the sixth-generation 10 nm node, known as 1c. The South Korean giant has confirmed that mass production of this memory is scheduled for the first half of the year, with the product reaching customers in the second half. Additionally, SK hynix claims that the speed of these LPDDR6 modules exceeds 10.7 Gbps, suggesting that the company is preparing some overclocked versions as well, surpassing the initial speed specifications of this LPDDR6 generation from JEDEC. If the previous International Solid-State Circuits Conference (ISSCC) 2026 show in San Francisco was an indication, SK hynix is preparing modules that will run at speeds of up to 14.4 Gbps, delivering a significant throughput boost over the previous-generation LPDDR5X memory. The company claims a 33% improvement over LPDDR5X, which topped out at 10.7 Gbps, aligning with the 14.4 Gbps figure for LPDDR6.

SK hynix is also expecting significant power efficiency optimizations exceeding 20% thanks to the new technologies enabling LPDDR6 to run. This generation of low-power DDR memory uses a sub-channel structure that allows the memory channels to operate selectively and only process necessary data paths, meaning not all channels need to be engaged when unnecessary. Additionally, LPDDR6 incorporates Dynamic Voltage and Frequency Scaling (DVFS), which optimizes power consumption and performance by dynamically adjusting the voltage/frequency curve depending on the scenario. SK hynix notes that during applications like gaming, DVFS will scale the frequency to achieve maximum bandwidth, while standard applications will see lower frequencies to balance power consumption.

Samsung is officially ending the production of its 2D NAND flash storage this year, and the company will be repurposing its old production lines to better fit the AI-driven demand. According to The Elec Korea, Samsung plans to officially stop 2D NAND production at its Hwaseong site, with Line 12 being the one carrying this aging technology. Instead of completely abandoning this facility, which houses plenty of chip-making tools, Samsung will repurpose them for DRAM metallization, which is the process of applying actual pathways within the DRAM itself to connect memory cells. Interestingly, the Hwaseong Line 12 holds a monthly wafer production capacity of 80,000 to 100,000 12-inch wafers. This is a significant number of wafers, which are now only used for 2D NAND Flash, a technology that is no longer needed in the wake of 3D NAND Flash technology.

Continuing the Line 12 legacy will be Samsung's 6th-generation 10 nm-class 1c DRAM, a technology used for HBM4, and Samsung expects the total wafer capacity for 1c DRAM to reach about 200,000 wafers per month in the second half of the year. Adapting the old 2D NAND Flash production site will definitely help, and Samsung will run this production along with Pyeongtaek Line 3 and Line 4.

Dai Nippon Printing Co., Ltd. (DNP) today announced the development of a nanoimprint lithography (NIL) template featuring a circuit line width of 10 nanometers (nm: 10-9 meter). The new template enables patterning for logic semiconductors equivalent to the 1.4 nm generation and meets the miniaturization needs of cutting-edge logic semiconductors used in devices such as smartphones, data centers, and NAND flash memory.

Background and Aims
In line with the shift to more sophisticated devices seen in recent years, demands have emerged for even greater miniaturization in cutting-edge semiconductors, leading to advances in Extreme Ultra-Violet (EUV) lithography-based production. EUV lithography, however, requires substantial capital investment, energy consumption, and operating costs in building production lines and the exposure process. This has fed into the pressing need to balance a reduction in manufacturing costs with a lowering in the environmental burden.

During the 2025 Korea Tech Festival in Seoul, Samsung's 40 Gbps GDDR7 memory received a presidential recognition medal. This next-generation memory chip is built on Samsung's 12 nm (10 nm class) DRAM node and operates at 40 Gbps with a 3 GB (24 Gb) capacity. This announcement follows Samsung's recent sampling of its fastest-ever GDDR7 memory, which runs at 36 Gbps. With a 24 Gb capacity per chip, this translates to 3 GB of capacity, designed for the next generation of graphics cards. These are not Samsung's only 3 GB modules. The South Korean company is also producing 28 Gbps 3 GB modules, which are now in mass production, likely for NVIDIA's upcoming mid-cycle SUPER refresh.

As 3 GB modules are uncommon, the confirmation of mass production, especially starting at 28 Gbps, is a welcome addition to faster VRAM options. However, with Samsung already testing 40 Gbps GDDR7 memory modules with 3 GB capacity, it will be interesting to see where these modules will be used. For NVIDIA's mid-cycle SUPER refresh of the GeForce RTX 50-series GPUs, the company is likely to use chips that are already in mass production, as the sampling stage alone is not sufficient for a product rollout. Ensuring a proper supply is crucial, so a proper stock of GDDR7 chips must pile up first.

Intel's Q3 earnings delivered a solid number, but a few interesting things are happening at Intel's Fabs that aren't related to any leading-edge node production. According to Intel CFO David Zinsner, "In Q3, Intel Foundry delivered Intel 10 and 7 volume above expectations," indicating that demand for Intel's products built on these nodes is significantly exceeding supply. Zinsner noted, "Capacity constraints, especially on Intel 10 and Intel 7, limited our ability to fully meet demand in Q3 for both data center and client products," suggesting strong demand for Core and Xeon processors built on these nodes.

Intel first introduced Intel 7 node, previously known as 10 nm Enhanced SuperFin, with 12th Generation "Alder Lake." However, that is now discontinued and Intel continues to ship 13th Generation "Raptor Lake" and 14th Generation Core "Raptor Lake Refresh" client CPUs on the Intel 7 node. For Xeon server chips, the company uses the Intel 7 node for the 4th Generation "Sapphire Rapids," 5th Generation "Emerald Rapids" Xeon Scalable and manufactures the I/O die for the latest "Granite Rapids" Xeon 6, where the compute dies are made on the Intel 3 node. High demand from the gaming sector for 13th and 14th Gen gaming CPUs, along with strong demand for Xeon processors, has created a manufacturing bottleneck. Intel will prioritize delivering data center products first and gaming products second.

SK hynix Inc. announced today that it has assembled the industry's first High NA EUV lithography system for mass production at the M16 fabrication plant in Icheon, South Korea. At an event to commemorate the assembly of the system, SK hynix's Head of R&D Cha Seon Yong, Head of Manufacturing Technology Lee Byoungki and ASML's Head of Customer Team SK hynix-Japan Kim Byeong-Chan celebrated the introduction of the equipment to produce next-generation DRAM.

The move lays the foundation for a swift development and supply of the cutting-edge products that meet customer demand amid intense competition of the global semiconductor industry. SK hynix aims to enhance credibility and stability of the global supply chain through close collaboration with business partners. A sophisticated process technology to scale memory cells is critical to advance productivity and product performance. A more sophisticated pattern leads to an increase in the number of chips produced from a wafer and an improvement in power efficiency and performance.

Samsung Electronics achieved a significant technological milestone by securing production readiness approval for its sixth-generation DRAM technology. Industry sources, as Korea Herald reports, confirmed on Tuesday that the company received internal authorization for mass production, marking completion of the advanced 10 nm-class process (called 1c DRAM) development. We recently reported that Samsung was able to achieve yield rates of 50-70% in testing for the 1c DRAM process as the company seems to be able to follow its projected timeline of approximately two years between product generations. The development holds particular significance for Samsung's high bandwidth memory (HBM) strategy since the company plans to commence HBM4 mass production during the second half of this year utilizing the newly developed sixth-generation DRAM technology. Samsung Electronics announced on May its adoption of hybrid bonding technology for future HBM4 memory stacks. The implementation aims to decrease thermal resistance while enabling ultra-wide memory interfaces, addressing the increasing bandwidth and efficiency requirements of artificial intelligence and high-performance computing applications.

SK hynix, currently dominating the HBM market pursues HBM4 development using fifth-generation DRAM technology and started to deliver HBM4 samples to major clients in March, targeting similar production timelines for the latter half of this year. However, Samsung faces critical qualification requirements ahead as the company must deliver HBM4 samples and successfully complete NVIDIA's qualification testing to secure high-volume supply contracts. Additionally, Samsung continues awaiting qualification approval for its 12-layer HBM3E product while supplying AMD and looking for supply agreements with NVIDIA.

Samsung has achieved better production results for its advanced memory technology, according to Sedaily, as cited by TrendForce. The company's sixth-generation 10 nm DRAM, called 1c DRAM, now shows yield rates of 50-70% in testing. This represents a significant improvement from last year's results, which were below 30%. Samsung takes a different path from its rivals, while SK Hynix and Micron stick with 1b DRAM technology for HBM4 products, Samsung opts to create the newer 1c DRAM. This choice comes with more risk; however, it might bring bigger rewards, as the improved production rates enable Samsung to expand its manufacturing operations. The company plans to increase 1c DRAM production at its Hwaseong and Pyeongtaek facilities with expansion activities expected to begin before the end of this year.

These developments also support Samsung's HBM4 production schedule since the company aims to begin mass production of HBM4 products later this year. Yet, experts in the field point out that the product is still in its early stages and needs ongoing monitoring. Samsung planned to begin mass-producing sixth-gen 10 nm DRAM by late 2024. Instead, the company chose to remake the chip's design. This decision caused delays of more than one year however it was made to achieve better performance and yields. The new DRAM products will be manufactured at Samsung's Pyeongtaek Line 4 facility as these chips will serve both mobile and server applications. Separately, HBM4-related production will take place at Pyeongtaek Line 3.

The vast majority of High Bandwidth Memory (HBM) new stories—so far, in 2025—have involved or alluded to new-generation SK hynix and Micron products. As mentioned in recently published Samsung Electronics Q1 financial papers, company engineers are still working on "upcoming enhanced HBM3E products." Late last month, a neighbor/main rival publicly showcased their groundbreaking HBM4 memory solution—indicating a market leading development position. Samsung has officially roadmapped a futuristic "sixth-generation" HBM4 technology, but their immediate focus seems to be a targeted sales expansion of incoming "enhanced HBM3E 12H" products. Previously, the firm's Memory Business has lost HBM3 ground—within AI GPU/accelerator market segments—to key competitors.

Industry insiders believe that company leadership will attempt to regain lost market shares in a post-2025 world. As reported by South Korean news outlets, Kim Jae-joon (VP of Samsung's memory department) stated—during a recent earnings call, with analysts—that his team is: "already collaborating with multiple customers on custom versions based on both HBM4 and the enhanced HBM4E." The initiation of commercial shipments is anticipated at some point in 2026, hinging on mass production starting by the second half of this year. The boss notified listeners about development "running on schedule." A Hankyung article alleges that Samsung HBM4 evaluation samples have been sent out to "NVIDIA, Broadcom, and Google." Wccftech posits a positive early outlook: "Samsung will use its own 4 nm process from the foundry division and utilize the 10 nm 6th-generation 1c DRAM, which is known as one of the highest-end in the market. On paper, (their) HBM4 solution will be on par with competing models (from SK hynix), but we will have to wait and see."

Ferroelectric Memory Co. (FMC) and Neumonda have formed a partnership to commercialize "DRAM+," a ferroelectric (FeRAM) memory architecture combining DRAM's speed with non-volatile data retention. The technology substitutes conventional capacitors with ferroelectric hafnium oxide (HfO₂) elements, allowing persistent storage without power while maintaining nanosecond access times. This hybrid technology addresses the performance gap between high-speed DRAM and storage-class memory like NAND flash. Unlike previous European DRAM ventures from Infineon and Qimonda that failed against commodity memory economics, FMC targets specialized applications valuing persistence and power efficiency. The HfO₂-based approach resolves limitations of previous FeRAM memory implementations using lead zirconate titanate (PZT) that couldn't scale beyond megabyte capacities.

Prototypes now demonstrate gigabit-range densities compatible with sub-10 nm fabrication of traditional DRAM made by Micron, Samsung, SK Hynix, and others. By eliminating refresh cycles, DRAM+ reduces static power consumption substantially compared to traditional one-transistor/one-capacitor DRAM cells. Primary applications include AI accelerators requiring persistent model weights, automotive ECUs with immediate startup requirements, and power-constrained medical implants. Neumonda will contribute its test platform suite Rhinoe, Octopus, and Raptor for electrical characterization and analytics at lower capital costs than standard semiconductor test equipment. No production timeline has been announced for commercial DRAM+ products.

Micron Technology, Inc., today announced it is the first in the industry to ship samples of its 1γ (1-gamma), sixth-generation (10 nm-class) DRAM node-based DDR5 memory designed for next-generation CPUs to ecosystem partners and select customers. This 1γ DRAM milestone builds on Micron's previous 1α (1-alpha) and 1β (1-beta) DRAM node leadership to deliver innovations that will power future computing platforms from the cloud to industrial and consumer applications to Edge AI devices like AI PCs, smartphones and automobiles. The Micron 1γ DRAM node will first be leveraged in its 16 Gb DDR5 DRAM and over time will be integrated across Micron's memory portfolio to meet the industry's accelerating demand for high-performance, energy-efficient memory solutions for AI. Designed to offer speed capabilities of up to 9200 MT/s, the 16 Gb DDR5 product provides up to a 15% speed increase and over 20% power reduction compared to its predecessor.

Nanya Technology's Board of Directors today has approved a strategic partnership with PieceMakers Technology, Inc. ("PieceMakers") to jointly develop customized ultra-high-bandwidth memory solutions. As part of the collaboration, Nanya Technology will subscribe to a cash capital increase of up to NT$ 660 million, purchasing up to 22 million common shares at NT$ 30 per share in PieceMakers. Upon completion of the capital increase, Nanya Technology is expected to acquire up to approximately 38% stakes of PieceMakers.

To meet the growing demand for high-performance memory driven by AI and edge computing, this collaboration will combine Nanya Technology's 10 nm-class DRAM innovation with PieceMakers' expertise in customized DRAM design to develop high-value, high-performance, and low-power customized ultra-high-bandwidth memory solutions, unlocking new opportunities in AI and high-performance computing markets.

As a quick follow-up to last week's "Arrow Lake-S" de-lidding by Madness727, we now have a line-up of a de-lidded Core Ultra 9 285K "Arrow Lake-S" processor placed next to a Core i9-14900K "Raptor Lake-S," and the Core i9-12900K "Alder Lake-S." The tile-based "Arrow Lake-S" is visibly larger than the two, despite being made on more advanced foundry nodes. Both the 8P+16E "Raptor Lake-S" and 8P+8E "Alder Lake-S" chips are built on the Intel 7 node (10 nm Enhanced SuperFin). The "Raptor Lake-S" monolithic chip comes with a die-area of 257 mm². The "Alder Lake-S" is physically smaller, at 215 mm². What sets the two apart isn't just the two additional E-core clusters on "Raptor Lake-S," but also larger caches—2 MB of L2 per P-core, increased form 1.25 MB/core, and 4 MB per E-core cluster, increased from 2 MB/cluster.

Thanks to high quality die-shots of the "Arrow Lake-S" by Madness727, we have our first die-area estimations by A Hollow Knight on Twitter. The LGA1851 fiberglass substrate has the same dimensions as the LGA1700 substrate. This is to ensure the socket retains cooler compatibility. Using geometrical measurements, the base tile of the "Arrow Lake-S" is estimated to be 300.9 mm² in area. The base-tile is a more suitable guideline for "die-area," since Intel uses filler tiles to ensure gaps in the arrangement of logic tiles are filled, and the chip aligns with the base-tile below. The base tile, built on an Intel 22 nm foundry node, serves like a silicon interposer, facilitating high-density microscopic wiring between the various logic tiles stacked on top, and an interface to the fiberglass substrate below.

SK hynix announced today that it has developed the industry's first 16 Gb DDR5 built using its 1c node, the sixth generation of the 10 nm process. The success marks the beginning of the extreme scaling to the level closer to 10 nm in the memory process technology. The degree of difficulty to advance the shrinking process of the 10 nm-range DRAM technology has grown over generations, but SK hynix has become the first in the industry to overcome the technological limitations by raising the level of completion in design, thanks to its industry-leading technology of the 1b, the fifth generation of the 10 nm process.

SK hynix said it will be ready for mass production of the 1c DDR5 within the year to start volume shipment next year. In order to reduce potential errors stemming from the procedure of advancing the process and transfer the advantage of the 1b, which is widely applauded for its best performing DRAM, in the most efficient way, the company extended the platform of the 1b DRAM for development of 1c. The new product comes with an improvement in cost competitiveness, compared with the previous generation, by adopting a new material in certain process of the extreme ultraviolet, or EUV, while optimizing the EUV application process of total. SK hynix also enhanced productivity by more than 30% through technological innovation in design.