Friday, March 6th 2020

AMD Sheds Light on the Missing "+" in "7nm" for Zen 3 and RDNA2 in its Latest Presentation

AMD at its Financial Analyst Day 2020 presentation made a major clarification about its silicon fabrication process. It was previously believed that the company's upcoming "Zen 3" CPU microarchitecture and RDNA2 graphics architectures were based on TSMC's N7+ (7 nm EUV) silicon fabrication process because AMD would mark the two as "7 nm+" in its marketing slides. Throughout its Financial Analyst Day presentation, however, AMD avoided using that marker, and resorted to an amorphous "7 nm" marker, prompting one of the financial analysts to seek a clarification. At the time, AMD responded that they were aligning their marketing with that of TSMC, and hence chose to use "7 nm" in its new slides.

It turns out that the next step to TSMC N7, the company's current-generation 7 nm DUV silicon fabrication node, isn't N7+ (7 nm EUV), but rather it has a nodelet along the way, which the foundry refers to as N7P. This is a generational refinement of N7, but does not use EUV lithography, which means it may not offer the 15-20 percent gains in transistor densities offered by N7+ over N7. AMD clarified that "7 nm+" in its past presentations did not intend to signify N7+, and that the "+" merely denoted an improvement over N7. At the same time, it won't specify whether "Zen 3" and RDNA2 are based on N7P or N7+, so the company doesn't rule out N7+, either. We'll probably learn more as we near the late-2020 launch of "Zen 3" as EPYC "Milan."
AMD CPU Roadmap Zen 3 Zen 4 AMD CPU Roadmap Zen 2 Zen 3
Source: AnandTech
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19 Comments on AMD Sheds Light on the Missing "+" in "7nm" for Zen 3 and RDNA2 in its Latest Presentation

#2
_Flare
N7 vs N7P
+7% Perf. or -10% Power

N7 vs N7+
+10% Perf. or -15% Power

fuse.wikichip.org/news/2567/tsmc-talks-7nm-5nm-yield-and-next-gen-5g-and-hpc-packaging/
N7P

TSMC has started rolling out an optimized version of their N7 process called N7 Performance-enhanced version (N7P). This process goes by various other names such as “2nd generation 7 nm” and “7 nm year 2”. This process should not be confused with N7+. N7P is an optimized, DUV-based, process which uses the same design rules and is fully IP-compatible with N7. N7P introduces FEOL and MOL optimizations which are said to translate to either 7% performance improvement at iso-power or up to 10% lower power at iso-speed.

N7+

TSMC’s N7+ is their first process technology to adopt EUV for a few critical layers. N7+ entered mass production last quarter (Q2). TSMC says they have demonstrated similar yield to N7. Compared to their N7 process, N7+ is said to deliver around 1.2x density improvement. N7+ is said to deliver 10% higher performance at iso-power or, alternatively, up to 15% lower power at iso-performance. On paper, N7+ appears to be marginally better than N7P. Though keep in mind that those improvements can only be obtained through a new physical re-implementation and new EUV masks.
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#4
Cheeseball
Not a Potato
EarthDog
2 Red X's here too @btarunr
Here dude in case you need to see them:


EDIT: @btarunr Need to update the forum-view of the post. It shows up fine on the front page (where I pulled the images from).
Posted on Reply
#5
Recus
2030 7nm++++++++++++

Intel stuck with 14nm, AMD 7nm. o_O
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#6
Flanker
_Flare
On paper, N7+ appears to be marginally better than N7P. Though keep in mind that those improvements can only be obtained through a new physical re-implementation and new EUV masks.
Cost savings in optical masks sounds pretty good.
Posted on Reply
#7
_Flare
Flanker
Cost savings in optical masks sounds pretty good.
Yeah, especially when no Zen3+ steps are required with getting an early N5 with Zen4 in 2021.
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#8
dicktracy
I just hope RDNA2 is somewhat competitive against Nvidia so they can give us more cuda cores, which is rumored to go upto 8k cores on the Tesla variant!
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#9
theoneandonlymrk
dicktracy
I just hope RDNA2 is somewhat competitive against Nvidia so they can give us more cuda cores, which is rumored to go upto 8k cores on the Tesla variant!
The relevance of your post is 0.1%

Troll much.
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#10
bug
So... the headline/article that says RDNA2 will be 50% more efficient still stands?
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#11
R0H1T
Yes, best case scenario (vs the most inefficient Navi?) I'd say why not.
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#12
medi01
"Mark Papermaster clarified in the Q&A section afterwards. TSMC are now just including N7+ in N7 as additional libraries, AMD are just following their nomenclature now. They're still 'N7+' products in that they use EUV for some layers "

Whatever the heck that means.
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#13
_Flare
medi01
"Mark Papermaster clarified in the Q&A section afterwards. TSMC are now just including N7+ in N7 as additional libraries, AMD are just following their nomenclature now. They're still 'N7+' products in that they use EUV for some layers "

Whatever the heck that means.
This could mean that N7P is not DUV only and eventually makes also use of EUV in some layers, but without the heavier changes to the IP wich would be necessary with N7+.
Or there is some sort of N7+-lite wich uses nearly no to none IP-breaking at all. So it would be like a mix of N7P and N7+, sort of.
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#14
ppn
7% ~ 300Mhz, so nice. 4.7Ghz is quite impressive. The first EUV is N6 perhaps next year.
Posted on Reply
#15
Vayra86
medi01
"Mark Papermaster clarified in the Q&A section afterwards. TSMC are now just including N7+ in N7 as additional libraries, AMD are just following their nomenclature now. They're still 'N7+' products in that they use EUV for some layers "

Whatever the heck that means.
It means what I predicted a year or so back, these nodes are coming about much slower than they are presented to us. A full EUV 7nm will deliver a far more powerful chip.

We will be riding 7nm for several years from today, make no mistake. Its an uphill battleand every baby step has to overcome yield and cost issues.

Now you also know why neither Intel or Nvidia was eager to early adopt 7nm.
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#16
mtcn77
They are using EUV only where it is not mission critical, but saves masking layers. They will be using it on copper contacts and all.
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#17
ppn
no crytical layers none of that. just simple N7P or direct shrink to N6 EUV that is specifically built to use the same design rules as DUV, for 18% better density. But I dont believe that N5 will ever be used by AMD, it requires different rules and redesigns. This N7P branch ends with N6, and the story ends there. Jumping from N7 to N5 or N3 after that is very unlikely. I mean what comes next 128 core, 256?, this would be insane core count.
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#19
Kaotik
AnandTech has apparently missed the fact that Navi10 is already N7P, so if it's "enhanced 7nm" compared to Navi10, it should be N7+ EUV (unless TSMC has different, newer libraries for N7P)
medi01
"Mark Papermaster clarified in the Q&A section afterwards. TSMC are now just including N7+ in N7 as additional libraries, AMD are just following their nomenclature now. They're still 'N7+' products in that they use EUV for some layers "

Whatever the heck that means.
N7+ uses EUV only for some layers, it's been known since TSMC told about the process years ago
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