Monday, December 11th 2023

Intel Demos 3D Transistors, RibbonFET, and PowerVia Technologies

During the 69th annual IEEE International Electron Devices Meeting (IEDM), Intel demonstrated some of its latest transistor design and manufacturing advancements. The first one in line is the 3D integration of transistors. According to Intel, the company has successfully stacked complementary field effect transistors (CFET) at a scaled gate pitch down to 60 nm. With CFETs promising thinner gate channels, the 3D stacked CFET would allow for higher density by going vertically and horizontally. Intel's 7 node has a 54 nm gate pitch, meaning CFETs are already close to matching production-ready nodes. With more time and development, we expect to see 3D stacked CFETs in the production runs in the coming years.

Next, Intel has demonstrated RibbonFET technology, a novel approach that is the first new transistor architecture since the introduction of FinFET in 2012. Using ribbon-shaped channels surrounded by the gate, these transistors allow for better control and higher drive current at all voltage levels. This allows faster transistor switching speeds, which later lead to higher frequency and performance. The width of these nanoribbon channels can be modulated depending on the application, where low-power mobile applications use less current, making the channels thinner, and high-performance applications require more current, making the channels wider. One stack of nanoribbons can achieve the same drive current as multiple fins found in FinFET but at a smaller footprint.
Next up, we learn that Intel has commented that its PowerVia technology is production-ready, with the first products utilizing PowerVia expected to arrive in 2024. PowerVia is Intel's efforts to change the structure of the transistor power delivery, moving the power routing wires from the top to below the transistor in an effort to manage power efficiently and not obscure signal wires found on the top of the transistor. PowerVia is formed into a backside power delivery network that operates without contact with the single network in the chip. The connection to the transistor layer is made using nano through silicon vias (TSVs), which are 500 times smaller than regular TSVs.
Intel has also demonstrated the integration of silicon and GaN. The company successfully established a high-performance, large-scale integrated circuit solution called "DrGaN" for power delivery. This solution can potentially enable power delivery solutions to keep pace with the power density and efficiency demands of future computing. Additionally, the company will also present transition metal dichalcogenide (TMD) 2D channel materials, which offer a scaling path for transistor physical gate length below 10 nm. Intel is scheduled to demonstrate prototypes of the CMOS design's high-mobility TMD transistors for NMOS (n-channel metal oxide semiconductor) and PMOS (p-channel metal oxide semiconductor) elements. Lastly, the company will also present the so-claimed world's first gate-all-around (GAA) 2D TMD PMOS transistor and the world's first 2D PMOS transistor fabricated on a 300 mm wafer, all dedicated to scaling transistor density further.
Sources: Intel, Intel (YouTube Video)
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57 Comments on Intel Demos 3D Transistors, RibbonFET, and PowerVia Technologies

#1
Assimilator
Now if only these innovations could make their CPUs decent. I'm not even asking for good here, just decent.
Posted on Reply
#2
lexluthermiester
AssimilatorNow if only these innovations could make their CPUs decent. I'm not even asking for good here, just decent.
What are you talking about?
Posted on Reply
#3
FoulOnWhite
AssimilatorNow if only these innovations could make their CPUs decent. I'm not even asking for good here, just decent.
You're making me want to cry for buying Intel /s
Posted on Reply
#4
ratirt
AssimilatorNow if only these innovations could make their CPUs decent. I'm not even asking for good here, just decent.
Intel's CPUs are decent just not the best in general or if you take all aspects of a CPU into account. These are good in one thing but lack somewhere else.
Posted on Reply
#5
AusWolf
I'll wait until BobaFET comes along.
Posted on Reply
#6
Kohl Baas
AusWolfI'll wait until BobaFET comes along.
Fancy some carbon, ehh?:roll:
Posted on Reply
#7
ExcuseMeWtf
But Intel just told us "new technology isn't always new". Or something like that. Or was it just supposed to apply to AMD?
Posted on Reply
#8
AusWolf
ExcuseMeWtfBut Intel just told us "new technology isn't always new". Or something like that. Or was it just supposed to apply to AMD?
I guess it means that "new technology is new when we want to sell it as new".
Posted on Reply
#9
Daven
Now if we can just get Intel to stop fabbing its own chips and use this technology to fab other companies’ chips.
Posted on Reply
#10
Denver
The problem is that lately Intel's revolution only happens on paper, I don't doubt that TSMC is closer to delivering the same advances mentioned.
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#11
Eternit
Nice slides... yet Intel booked TSMC for Lunar Lake computing tiles.
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#12
ymdhis
Incredible how much they can do while still being stuck on 14nm++++++++++++++++++++.
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#13
ExcuseMeWtf
ymdhisIncredible how much they can do while still being stuck on 14nm++++++++++++++++++++.
They aren't though.
Posted on Reply
#15
Hyderz
AusWolfI'll wait until BobaFET comes along.
Manufactured with the highest beskar quality
Posted on Reply
#16
ymdhis
ExcuseMeWtfThey aren't though.
I suppose the joke went over your head.
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#17
Wirko
CFET isn't 3D. It's 2.2D or 2.3D at best. Three dee would mean tens of layers and up.

But this is not to say it isn't a very interesting development. It is. Just like 3D DRAM, which could come to market in a couple years.
Posted on Reply
#18
ExcuseMeWtf
ymdhisI suppose the joke went over your head.
It wasn't a very good joke then.
Posted on Reply
#19
phanbuey
This is cool and all but they still have a culture of marketing stunts and business shenanigans over engineering.

If Pat can't reign that in we will just watch them collapse like an old flan.
Posted on Reply
#20
FoulOnWhite
ymdhisIncredible how much they can do while still being stuck on 14nm++++++++++++++++++++.
I think that joke/jibe is older than dinosaur poo now.

The most interesting development is PowerVia
Posted on Reply
#21
Wirko
FoulOnWhiteI think that joke/jibe is older than dinosaur poo now.

The most interesting development is PowerVia
Whatta didda you saya?

Posted on Reply
#22
Steevo
TSVs were already a thing, making them smaller by more trips through etch and mask only makes them more expensive and prone to defects/failure.

The ribbon FET seems like a good way drive interfaces with better termination and less chance of killing intermediate steps in the communication hub, but most of that could be solved by chiplets on a larger process anyway thats cheaper.
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#23
bonehead123
Can someone please wake me up when all this "intelovation" makes their chips better, faster, AND way less $$ than they are now..:roll:..:D....:shadedshu:

Cause till that happens.....y/A/w/N.....
Posted on Reply
#24
TechPope
Video shown is already from 2 years ago - youtube.com/watch?v=Rt-7c9Wgnds

Impressive nonetheless.
Posted on Reply
#25
Prima.Vera
lexluthermiesterWhat are you talking about?
I think he means power consumption wise.
Posted on Reply
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