Monday, July 14th 2025
AMD "Zen 6" Processor Families to Use a Mix of TSMC N2 and N3 Nodes
AMD's upcoming Zen 6 CPU family will leverage a combination of TSMC's N3 and N2 process nodes, according to slide decks shared with engineers at three leading motherboard vendors. These documents outline five distinct silicon lines set to arrive in late 2026 across servers, desktops, and notebooks. On the server front, the EPYC "Venice" lineup splits into Venice classic for general‑purpose deployments and Venice dense for high‑density cloud racks. Both variants use TSMC's custom‑tuned N2P process, offering an 8-10% clock‑speed boost over today's N3E. At the same time, each classic die grows to 12 Zen 6 cores, and each dense die houses 32 Zen 6c cores, enabling up to 256‑core, 512-threaded dense packages when eight dies are interconnected via the existing organic interposer.
For client systems, AMD has adopted codenames that hint at their intended usage profiles. "Olympic Ridge" will drive the Ryzen 10000 desktop series on the N2P node, while "Gator Range" targets gaming laptops exceeding 55 W. The mainstream thin‑and‑light segment will be served by "Medusa Point," featuring a hybrid design that pairs an N2P compute tile with an N3P I/O tile, with entry‑level models opting for a cost‑efficient monolithic N3P die. A more detailed "Medusa Halo" and the budget‑oriented "Bumblebee" series are also in the roadmap, though their process assignments remain under review. AMD and TSMC's close co‑optimization of metal layers and libraries means the final silicon closely resembles an "N2‑AMD" stack rather than a standard N2P node. First silicon is expected back from the fab before Christmas, with volume ramps timed for the back‑to‑school 2026 notebook cycle and a subsequent server refresh wave.
Sources:
Kepler_L2 on AnandTech Forums, via ComputerBase
For client systems, AMD has adopted codenames that hint at their intended usage profiles. "Olympic Ridge" will drive the Ryzen 10000 desktop series on the N2P node, while "Gator Range" targets gaming laptops exceeding 55 W. The mainstream thin‑and‑light segment will be served by "Medusa Point," featuring a hybrid design that pairs an N2P compute tile with an N3P I/O tile, with entry‑level models opting for a cost‑efficient monolithic N3P die. A more detailed "Medusa Halo" and the budget‑oriented "Bumblebee" series are also in the roadmap, though their process assignments remain under review. AMD and TSMC's close co‑optimization of metal layers and libraries means the final silicon closely resembles an "N2‑AMD" stack rather than a standard N2P node. First silicon is expected back from the fab before Christmas, with volume ramps timed for the back‑to‑school 2026 notebook cycle and a subsequent server refresh wave.
70 Comments on AMD "Zen 6" Processor Families to Use a Mix of TSMC N2 and N3 Nodes
And Gator Range is right up there with Alligator Alcatraz in my mind.. god I hate the internet sometimes lol.. but if it were me I would change that name..
@AleksandarK I don’t think the math checks out on this for non-dense configs, chief. You may want to reword this. And it would also be a downgrade compared to Turin since that already has 16x8 configs.
Graphics cards where, unfortunately, AMD is very weak and lost momentum and focus.
If AMD decides to return to the 65 - 95 W TDPs, you say bye to the "huge" performance jump.
It will be nice to see what the IO die upgrades get moving to 3nm from 6nm. Hopefully the ability to use CUDIMM and being able to use 9000mhz DDR5 is going to be essential to feed the extra cores per CCD otherwise those extra cores are going to be handicapped by the lack of memory bandwidth.
I hope the APUs are on 2nm so they get the most performance out of the possible GPU being equipped on those dies! I am just waiting for 24 core 2048+ Shaders and LPCAMM possibly in a Steamdeck format. I personally would be tempted with a 12 core 1536 shader part myself as I believe that would be enough for handhelds/emulating for a couple of years.
Even then theyll be hard to find. HX370 laptops with DDR5X memory are like hens teeth, as are mini PCs.
These will not be easy to cool.
Making their socket backwards compatible with AM4 coolers was the dumbest thing AMD did here....
AM5's IHS is absurdly think, done to preserve socket AM4 compatibility and its the single biggest thing holding thermals back.