Monday, March 16th 2026

AMD Zen 6 "Medusa Point" CPU Spotted on Geekbench with 10 Cores, 32 MB L3 Cache

A fresh leak from Geekbench has surfaced listing an unannounced AMD processor with the OPN (Ordering Part Number) code 100-000001713-31. As for the platform, that is listed as Plum-MDS1, a somewhat direct hint to Medusa Point, AMD's next-gen mobile APU family based on Zen 6. The chip is a 10-core, 20-thread with a 2.4 GHz base clock, though actual test results show it running closer to 1.3-2 GHz, unsurprising for an engineering sample this early in development. Each core gets 1 MB of L2 cache, and the L3 comes in at 32 MB, up from 24 MB on Strix Point and 16 MB on Hawk Point. This is 50% more cache than the current 10-core parts like the Ryzen AI 9 365. The test system had 32 GB of memory installed, type unspecified. Benchmark numbers aren't worth reading into at this stage, as the chip spent most of the test hovering around 1.39 GHz and barely peeked above 2 GHz, well below what a final retail part on a 3 nm process would run at. Too early to draw any conclusions from the scores.

Shipping manifests from Planet3DNow linked to the "Medusa" codename suggest a 4C+4D layout, standard and density-optimized cores, though that doesn't exactly explain the 10-core count seen in Geekbench. One theory is that two additional low-power cores sit in the IO die, bringing the total to ten. The part is expected to be a 28 W TDP mobile chip for the FP10 socket. Medusa Point is shaping up to combine Zen 6 CPU cores with a mix of RDNA 5 and RDNA 3.5 graphics, plus an updated NPU. A launch around CES 2027 fits the AMD usual cadence, meaning there is likely a long wait ahead; however, this Geekbench entry confirms that testing is already happening, whether at AMD itself or at one of its early hardware partners.
Sources: VideoCardz, BenchLeaks, Planet3DNow
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12 Comments on AMD Zen 6 "Medusa Point" CPU Spotted on Geekbench with 10 Cores, 32 MB L3 Cache

#1
Exilarch
The test system had 32 GB of memory installed, type unspecified.
They should probably test it with 64 GB of memory, but couldn't afford it.
Posted on Reply
#2
windwhirl
Nomad76Medusa Point is shaping up to combine Zen 6 CPU cores with a mix of RDNA 5 and RDNA 3.5 graphics, plus an updated NPU.
I legit wonder what's the reason for mixing up different GPU architectures.
Posted on Reply
#3
dgianstefani
TPU Proofreader
windwhirlI legit wonder what's the reason for mixing up different GPU architectures.
Old = cheap.

Same reason AMD is releasing RDNA 2/3/3.5 CPU/APUs in 2026.
Posted on Reply
#4
Nomad76
News Editor
windwhirlI legit wonder what's the reason for mixing up different GPU architectures.
Possible scenarios: RDNA 5 for higher SKUs, RDNA 3.5 for lower (likely). Or just RDNA 5 (possible) or :roll: just RDNA 3.5 (not very likely). Reason(s)? anything such as yields, tech issues, pricing strategy and so on..
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#5
windwhirl
dgianstefaniOld = cheap.

Same reason AMD is releasing RDNA 2/3/3.5 CPU/APUs in 2026.
Ahh, I read the article as in this particular 10-core CPU would come with both RDNA3.5 and RDNA5 CUs in the same die
Posted on Reply
#6
Thunderslat
Are we sure it's RDNA 3.5 and not RDNA 4m (whatever that is)? It does seem stupid but I guess they figure anyone interested in gaming will be using a dGPU anyway. Not that I would recommend they keep using old iGPU's.
Posted on Reply
#7
ymdhis
ThunderslatAre we sure it's RDNA 3.5 and not RDNA 4m (whatever that is)? It does seem stupid but I guess they figure anyone interested in gaming will be using a dGPU anyway. Not that I would recommend they keep using old iGPU's.
Previous leaks said that the internal docs have mixed references to RDNA 3.5/4/5. So the truth is: we don't know until it is released.
It could be either, or the 4m thing which is 3.5 with maybe one or two extra improvements for AI and a more PR friendly name.
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#8
GenericUsername2001
windwhirlI legit wonder what's the reason for mixing up different GPU architectures.
I think that might be a bit of a mis-phrasing; from the rumors/leaks I have seen the Zen 6 Medusa Point chips will be getting modest, older RDNA 3.something graphics, and the Zen 6 Medusa Halo and Medusa Halo mini will be getting quite large (48 CU or 24 CU) RDNA 5 based iGPUs. Basically AMD will have big, full featured iGPUs for customers who want them, but also have smaller, cheaper, less featured iGPUs for products that don't need much iGPU power. No sense in putting a giant iGPU in a gaming laptop that is also equipped with a discrete card, for example.
Posted on Reply
#9
lambda
GenericUsername2001I think that might be a bit of a mis-phrasing; from the rumors/leaks I have seen the Zen 6 Medusa Point chips will be getting modest, older RDNA 3.something graphics, and the Zen 6 Medusa Halo and Medusa Halo mini will be getting quite large (48 CU or 24 CU) RDNA 5 based iGPUs. Basically AMD will have big, full featured iGPUs for customers who want them, but also have smaller, cheaper, less featured iGPUs for products that don't need much iGPU power. No sense in putting a giant iGPU in a gaming laptop that is also equipped with a discrete card, for example.
Or could be some custom silicon for the iGPU which might be some additional features baked on top of RDNA 3.x

I haven't looked at the leaks so just guessing.
Posted on Reply
#10
Alpha_Lyrae
One of the better things about AMD's IPs is that VCN and DCN can be implemented separately from GPU uArch, so VCN/DCN 4.0.1+ can be implemented into Zen 6's IOD to modernize the display and media engines, as this IOD will be around until the end of AM5 (whenever DDR6 is available for AM6). With DCN 4.0.x, iGPUs would also gain RIS2, so there's a high likelihood this updated IOD has gfx1170 or RDNA 3.75 (it's close enough with fp8 dot4 - basically fp8 DP4a - in ISA and conversion instructions for WMMA/SWMMAC FP8/BF8) or "RDNA4m". Yep, it supports sparsity, which makes Redstone support more likely.

iGPU will only be important in mobile and for those who use dGPU passthrough via iGPU's display engine (RIS2 is built into display engine so non-RDNA4 dGPU owners can get an upgrade by using passthrough). For everyone else with a dGPU, you can transcode videos on both GPUs to use otherwise wasted silicon.

"Halo" parts will eventually get RDNA5 (gfx13xx) mobile, while gfx11xx remains on mainstream APUs to maintain an optimized die-area iGPU that's important in keeping costs down.
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#11
igormp
Alpha_LyraeOne of the better things about AMD's IPs is that VCN and DCN can be implemented separately from GPU uArch
Isn't that the case for most/all media (de|en)coder IPs?
Posted on Reply
#12
XeonsNOpterons
Cool leak to see this far out! However, the clock speeds are likely incorrectly reported. A later leak shows a maximum boost of 3.4GHz on Geekbench 6. Zen 6 is very likely going to bring only 12-18% IPC uplift over Zen 5, not 100% like some people are claiming by the misreported clock speed. Using the 3.4GHz boost from the other leaked benchmark, you are looking at this IPC difference in Geekbench 6:

Ryzen 9 9900X: ~3477 single core score / 5.65GHz = 615 SC/GHz (Zen 5)
10 core Zen 6: ~2241 single core score / 3.4GHz = 659 SC/GHz (Zen 6)

This is about a 7% IPC gain.
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