Wednesday, April 29th 2026

Intel Prepares HBM Killer: HB3DM Memory Stacks with Z-Angle Technology

Intel and SoftBank, through their subsidiary Saimemory, have been developing an alternative technology to the popular high-bandwidth memory (HBM) to provide more bandwidth and capacity for memory modules used with powerful AI accelerators. At VLSI 2026 in June, Saimemory is scheduled to present a paper on the newly developed HB3DM memory, which is based on Z-Angle Memory (ZAM) technology. This name refers to the vertical (Z-axis) stacking of dies, similar to traditional HBM. However, Intel aims to achieve impressive results using state-of-the-art manufacturing technology. The first generation of HB3DM will feature a total of nine layers, stacked using a hybrid bonding technique for 3D chip placement. At the base will be a logic layer that manages data movement within the chip, with eight DRAM layers on top for data storage. Each layer will include about 13,700 TSVs for hybrid bonding.

In terms of capacity, HB3DM will offer about 1.125 GB per layer, translating to 10 GB per memory module. Intel can achieve approximately 0.25 Tb/s of memory bandwidth per mm², and for a 10 GB module with a 171 mm² die area, we can expect around 5.3 TB/s per module. These impressive figures could quickly overshadow competing HBM4 memory, as HB3DM offers much higher bandwidth. HBM4 provides speeds of around 2 TB/s per stack, less than half of what HB3DM will deliver. However, HB3DM is limited by capacity, with only 10 GB available, whereas HBM4 can reach up to 48 GB per stack. Intel may increase the number of layers in production as HB3DM progresses, but for now, it is emerging as a bandwidth leader.
We don't yet know when Saimemory will launch these memory chips or who will manufacture the underlying DRAM. However, with Intel's involvement, there might be a return to DRAM manufacturing at Intel's fabs, although the specific node is currently unknown. As VLSI 2026 approaches, we expect to hear more details from both Intel and SoftBank about their Saimemory subsidiary and the progress they've made. Saimemory also plans to have prototypes ready by early 2028, with commercial products following in 2029.
Source: via Ian Cutress on X
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21 Comments on Intel Prepares HBM Killer: HB3DM Memory Stacks with Z-Angle Technology

#1
lambda
Volume production seems years away.
Posted on Reply
#2
kondamin
lambdaVolume production seems years away.
I hope not, it needs to be on the market before hbm5
I would love to see it on package for consumer soc's
Posted on Reply
#4
zenlessyank
If they slap 128 gigs on a 16-24 core CPU, I would gladly buy it. Maybe even have 3 tier with 32, 64, and 128 Gig sku's.

That shortened path set should drop latency by a lot.

I mean this for regular consumers, not servers, since that is already available in form.
Posted on Reply
#5
theonlyrobert
Wow, I can't wait to never see this come to consumer markets!
Posted on Reply
#6
kondamin
TumbleGeorgeWhy am I not impressed in any way?
Because we can't see any practical products on the shelves with benchmarks?
Posted on Reply
#7
close
kondaminBecause we can't see any practical products on the shelves with benchmarks?
Or because the last time they came up with some killer tech (back then, NAND killer), Optane, they managed it so well, Intel style.

Also "for memory modules used with powerful AI accelerators"... Let's see if they move slow enough to entirely miss the AI craze. I mean it's Intel and SoftBank, if anyone can do it it's them.
Posted on Reply
#8
igormp
zenlessyankIf they slap 128 gigs on a 16-24 core CPU, I would gladly buy it. Maybe even have 3 tier with 32, 64, and 128 Gig sku's.

That shortened path set should drop latency by a lot.

I mean this for regular consumers, not servers, since that is already available in form.
For regular consumers the latency on those should be really bad when compared to regular DDR memory, not sure if it'd make sense other than SoCs with big iGPUs that need to be kept fed.
Posted on Reply
#9
Visible Noise
lambdaVolume production seems years away.
When the joint venture was created in 2025 the production target was 2029 - 2030.
closeOr because the last time they came up with some killer tech (back then, NAND killer), Optane, they managed it so well, Intel style.

Also "for memory modules used with powerful AI accelerators"... Let's see if they move slow enough to entirely miss the AI craze. I mean it's Intel and SoftBank, if anyone can do it it's them.
And the University of Tokyo?
PSMC?
Shinko Electric Industries?
Sandia national laboratories?
Lawrence Livermore national laboratory?
Los Alamos national laboratory?
NEDO?
RIKEN?

It’s hilarious when low information posters don’t bother doing the tiniest bit of research before expressing their opinion about technology that they have no awareness of.
Posted on Reply
#10
Wirko
By using shingled stacks, Intel could pack as many dies as needed on a package, depending on the angle. Yes, this was my first thought when I saw the keyword "Angle".
zenlessyankThat shortened path set should drop latency by a lot.
Latency due to the signal path length is not negligible but it's not huge either. It's about 0.05 ns per cm each way, or 0.1 ns per cm both ways.
Posted on Reply
#11
lexluthermiester
lambdaVolume production seems years away.
Not really. If they're talking about it in such detail now it means they are nearing release readiness. I predict 1 year for production runs.
TumbleGeorgeWhy am I not impressed in any way?
Perhaps you do not understand what you're looking at nor how the benefits will play out(and that is not meant in an insulting way). With this kind of memory development, processor(any) performance can improve in a significant way, perhaps even dramatically so.
WirkoBy using shingled stacks, Intel could pack as many dies as needed on a package, depending on the angle. Yes, this was my first thought when I saw the keyword "Angle".
I was thinking something like this too!
WirkoIt's about 0.01 ns per cm each way, or 0.011 ns per cm both ways.
The above is more accurate. Remember, electrons move at the speed of light though circuit pathways. Circuit length latency is simply not the limitation most people think it is. The key problem is resistance over pathway distance that can cause latency. This requires careful attention to material purity and lithography precision.
Posted on Reply
#12
Intelko
TumbleGeorgeWhy am I not impressed in any way?
Because you're a depleted coomer?
Posted on Reply
#13
Apocalypsee
I hope RAMBUS will not come sniffing for some patent trolling
Posted on Reply
#15
lambda
lexluthermiesterNot really. If they're talking about it in such detail now it means they are nearing release readiness. I predict 1 year for production runs.
It's in the article, and those claims are usually pretty aggressive

> Saimemory plans to have prototypes ready by early 2028, with commercial products following in 2029.
Posted on Reply
#16
Prima.Vera
TumbleGeorgeWhy am I not impressed in any way?
Because this will never be used for average Joe, only for professional use.
Posted on Reply
#17
Octopuss
Refresh my memory (lol), isn't HBM what briefly appeared on some AMD cards and then failed due to.. reasons?
Posted on Reply
#18
TumbleGeorge
Prima.VeraBecause this will never be used for average Joe, only for professional use.
For average Joe have good news. A lot of previously reserved production capacity for data center memory should be freed up.
Posted on Reply
#19
lexluthermiester
lambdaIt's in the article, and those claims are usually pretty aggressive

> Saimemory plans to have prototypes ready by early 2028, with commercial products following in 2029.
I deliberately glossed over that. They're being conservative.
Posted on Reply
#20
close
Visible NoiseAnd the University of Tokyo?
PSMC?
Shinko Electric Industries?
Sandia national laboratories?
Lawrence Livermore national laboratory?
Los Alamos national laboratory?
NEDO?
RIKEN?

It’s hilarious when low information posters don’t bother doing the tiniest bit of research before expressing their opinion about technology that they have no awareness of.
What about them? Would it kill you to put a verb in there? And what does the Pagosa Springs Medical Center doing between all the others in the list? /s You know what, don't answer.

Name checks out though. Noise. Visible.
Posted on Reply
#21
Visible Noise
closeWhat about them? Would it kill you to put a verb in there? And what does the Pagosa Springs Medical Center doing between all the others in the list? /s You know what, don't answer.

Name checks out though. Noise. Visible.
You still didn’t bother to look it up lol.

The above are all the organizations developing this memory. Sandia has already validated the design.

You do know what the Sandia National Laboratories is, right? On second thought I shouldn’t assume that either.

www.sandia.gov/research/news/from-early-rd-to-mature-technology/
Posted on Reply
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