At the VLSI Symposium held in Hawaii, Intel unveiled the new Intel 18A-P foundry node, a significant refinement of the Intel 18A node that carves out room for a 9% increase in performance at iso-power. The company announced that it commenced risk-production on this new node, and has earmarked it for its next-generation Xeon "Diamond Rapids" server processor. Besides 9% increase in performance at iso-power, Intel 18A-P is claimed to offer an 18% power reduction at iso-performance, a 20-40% improvement in die-level thermal resistance, and a 10-30% improvement in Via resistance in performance-critical layers.

The company detailed the physical changes to the Intel 18A node made to achieve these gains. Intel added new cell options across its 180HP and 160HD libraries to support a wider range of products. For low-power designs, it introduced W1 and W1.5 cells. For high-performance needs, it added the W3P cell, which utilizes a "dual contact" design to boost performance without exceeding the footprint of the existing W3 cell. The company significantly lowered thermal resistance by integrating a new heat-conducting material on the front side of the die. Intel also updated its EDA tools to support thermally-aware layouts, allowing designers to better manage heat dissipation at the structural level.The first product to implement Intel 18A-P will be the next-generation Xeon 7 "Diamond Rapids" server processor, specifically, its Compute tiles. "Diamond Rapids" is built on the same philosophy as AMD EPYC, that CPU cores should be spun off to relatively small chiplets built on an advanced foundry node, connected to centralized I/O resources, for a mostly uniform memory latency to each CPU core."Diamond Rapids" features four Compute tiles, also known as "core building blocks" (CBBs) each built on the Intel 18A-P foundry node. Each Compute tile packs a CPU complex with 48 "Panther Cove" P-cores, and L3 cache localized to the tile. The total package CPU core count is 192, the core lacks SMT, making this a 192-core/192-thread processor.The four Compute tiles talk to two I/O and Memory Hub (IMH) tiles built on an older foundry node such as Intel 3. Each of the two IMH tiles has an 8-channel DDR5 memory interface, for a total of 16 DDR5 memory channels on the package. This is also Intel's first processor to implement PCI-Express Gen 6, which doubles bidirectional bandwidth over the current PCIe Gen 5. The company hasn't revealed the PCIe lane counts.

"Diamond Rapids" is built on a very large substrate, it introduces the new LGA9324 socket with an enormous pin-count.

The Xeon 7 "Diamond Rapids" family is slated for a 2027 market debut.