Thursday, June 18th 2026
AMD Ryzen Threadripper TR6 "Mustang Peak" Arrives with "Zen 6" and PCIe 6.0
AMD, through its official documentation portal, has confirmed the arrival of the next-generation Ryzen Threadripper TR6 "Mustang Peak" platform, along with some intriguing details about the upcoming CPU lineup. Based on the "Zen 6" CPU architecture, AMD is incorporating the latest I/O standards for these workstation powerhouses, including PCIe 6.0 and DDR5. As the "Zen 6" CPU cores are manufactured on TSMC's 2 nm semiconductor node, we expect AMD to increase the core count over its previous "Zen 5" Ryzen Threadripper workstation platform and deliver a significant performance boost due to advancements in node and microarchitecture. While specific details like TDP, clock speed, core counts, and segmentation are still lacking, we have learned that AMD is retiring its TR5 socket in favor of the new TR6 socket that will accommodate the platform.
With the introduction of PCIe 6.0, which doubles the bandwidth of PCIe 5.0 per lane configuration, AMD needs to add more pins to handle the increased bandwidth. Additionally, with varying core counts and clock speeds, the CPU socket likely requires more electrical capacity to support the new platform, necessitating an overhaul. If readers recall, the previous TR5 socket used 4,844 pins. For the TR6 update, it is possible that the pin count could exceed that number.
In previous leaks, we learned that "Zen 6" increased the core count to 12 cores per CCD. This is an improvement over the 8 cores per CCD that "Zen 5" currently offers in non-dense configurations. If the CPU maintains its maximum configuration of 12 CCDs, it would result in 144 cores and 288 threads, which is 50% higher than the 96-core, 192-thread configuration of the AMD Ryzen Threadripper 9995WX. AMD's documentation did not suggest any launch date, indicating that we are still months away from the actual release. AMD is likely to start shipping the first "Zen 6" CPUs in the form of server EPYC SKUs, followed by consumer Ryzen, with the HEDT platform being released later.
Source:
InstLatX64 on X
With the introduction of PCIe 6.0, which doubles the bandwidth of PCIe 5.0 per lane configuration, AMD needs to add more pins to handle the increased bandwidth. Additionally, with varying core counts and clock speeds, the CPU socket likely requires more electrical capacity to support the new platform, necessitating an overhaul. If readers recall, the previous TR5 socket used 4,844 pins. For the TR6 update, it is possible that the pin count could exceed that number.
29 Comments on AMD Ryzen Threadripper TR6 "Mustang Peak" Arrives with "Zen 6" and PCIe 6.0
maybe if you are doing some heavy AI work with 2 5090's or something but for the rest PCI-e 5 is overkill already.
They've not yet said anything about Zen 6 laptops. USB 4 maybe will appear? I don't know a lot about v4 though.
The chiplet is said to be 7% larger than Zen 5 chiplets. So it'll be a tight fit to get 12 chiplets on one package, but does sound doable.
Much Success!
In the past AMD removed PCIe 4.0 support for older series chipset motherboards.
Which would make the upgrade worthwhile for me.
Additionally:
If they were give PCIe gen 6 for the AM5, then it would be the solution to have "more" PCIe lanes directly to the CPU
Since PCIe gen 6 stuff will not come to the consumer sector for years.
Even if that would be only the "main" 16× PCIe connector connect to a switch to break it down to 2×16 PCIe gen 5 would be awesome! :love:
Then I would also get a new mainboard to enjoy that!I agree it would be nice to have, but it is mostly okay, and the people who need that much connectivity, already owning some Threadripper setup :D
I would rather buy a car
They will also probably consider enterprise grade SSDs, probably U.2, U.3, etc., which are far easier to cool and can handle high sustained loads unlike consumer grade drives.
What would be more usefull is decent total amount of lanes from platform because of M.2 storage hogging them.
While PCIe "host" and client" start from one lane and negotiate it up and even single PCIe lane would have plenty of bandwidth for normal storage needs, we can't split PCIe lanes of M.2 slots and PCIe slots are getting rare.
On your comment:
That is true, but don't forget: n line of gen 6 lanes = 2×n line of gen 5 lanes with a switch, why am I saying this?
The physical limitations of the AM5 (LGA 1718), with 1718 connector pins: you cannot have more lanes.
A transition to AM6 would mean a total platform redesign, which is costly. Given AMD's track record with long-lived sockets, I don't expect a change in the consumer desktop segment for at least another 3–4 years.
Regardless, awesome to see the name and that it is already in the works from AMD! Excited to see a Mustang Peak/Coral Rapids-WS showdown in late 2027, early 2028!
What is different here is a ryzen launch without memory bundles for cost controls falls flat at almost any cpu price. I appreciate microcenter bundles but most dont get them. :(
I don't know what the right play is here, they are now part of the reason why the market sucks. They are taking advantage of the pricing structure rather than attempting to keep the consumer market alive for after the bubble bursts.
From a company standpoint, epyc before ryzen makes sense, due to the market constriction, the price is the price and companies will buy as much as they can afford, everything will sell.
Consumers it's a want not a need, and we will wait it out, or buy as little as we can if there is a need.
This also leads to a weird scenario where, if we assume that Zen 7 will be paired with DDR6, the next Zen 6 TR might be on a new socket, and sTR6 will only have a single CPU generation available to it, similar-ish to sTRX4 (3000 TR non-Pro).
I also wonder if we will finally see TR with V-cache. The core count, PCIe lanes, and high-clocks paired with V-cache would make those HPC/CFD beasts.It could, but I bet that it'll not. PCIe version support is entirely dependent on the CPU, and has nothing to do with the chipset, fwiw.
Adding support for PCIe would mean AMD coming with a new IOD that has said support (and which works on the current pin arrangement of AM5), as well as new motherboards with the proper traces, retimers and lots of other signaling ICs that might be required to support the new version, which has extra costs, but that's pretty independent from the chipset itself.
The extra cost is likely not worth it given that there are no consumer devices available for PCIe 6.0, it would be way more expensive than the already expensive options we have, and consumers are not really saturating PCIe 5.0's bandwidth yet for it to be a problem.
With all of the above said, current AM5 motherboards would likely not be able to support PCIe 6.0, not even 8xx ones, due to the lack of proper traces and signaling ICs. Some might support it, but it's unknown which ones will and if it'll require hacks or anything of the sorts.
We saw this happening with AM4 btw, 1000 and 2000 series Ryzen had only PCIe 3.0 support, Ryzen 3000 brought PCIe 4.0 support alongside the B550/X570 chipsets, but some B450/X470 motherboards managed to have PCIe 4.0, some of which had this support removed on later firmware updates, as @A Computer Guy mentioned . Others you were able to hack support, but it was not stable, likely due to the missing traces/signaling stuff.
On AM5 some motherboards/chipsets do not support PCIe 5.0, but that's kind of an "artificial" limitation, since all the CPUs for that socket do have PCIe 5.0 support, so it's a matter of the lack of robust traces/signaling peripherals, or purely a firmware limitation.That would be indeed nice. I don't think the non-Pro TRs make much sense apart from the artificial price segmentation. If the non-Pro prices were way lower, enough for it to be an actual feasible HEDT platform for consumers, maybe even with UDIMM support instead of RDIMM, then it'd make more sense.Even then it's not really useful since 5090s are still PCIe 5.0. Maybe when the next gen GPUs come in with PCIe 6.0 support it'd make sense when you have 4~8 of those.
FWIW, with only two GPUs even PCIe 4.0 x8/x8 is more than enough (as long as you have PCIe P2P enabled for low latency comms).Given that it's a new, likely larger socket, a larger package would make sense.I agree that this would be pretty cool, but those are usually hella expensive. A switch just takes a PCIe upstream link and acs as a "hub" with as many ports as supported, sometimes with a total downstream bandwidth even higher than the upstream link. This is how part of the chipset in motherboards act as, and there are also dedicated boards with switches, see this c-payne example, which has 5 PCIe 4.0 x16 slots but only a single x16 upstream link, meaning that devices can communicate with one another at full bandwidth, but communication back to the upstream ends up being a bottleneck:
c-payne.com/products/pcie-gen4-switch-5x-x16-microchip-switchtec-pm40100
Aliexpress does have some switches available as well, but the 5.0 ones are well over $1k and have a limited amount of outputs. There're a couple of nice reddit posts about those switches + P2P for LLM usage:
LocalLLaMA/comments/1pt0av6/plxpex_pcie_40_seems_to_help_for_llms_and_p2p_ieLocalLLaMA/comments/1qeimyi/7_gpus_at_x16_50_and_40_on_am5_with_gen54
The current mobos that offer the option to do x8/x8 just have a simple mux, but even then they're way more expensive than the ones with just a single x16 slot. Adding such a switch would be even more expensive (and complex to implement). And given how expensive the current PCIe 5.0 switches are, I don't even want to imagine the cost for 6.0 ones :laugh:
And who knows for the next generation of Nvidia GPUs, they might feature it too.
We’re just asking for all that theoretical bandwidth to be broken up into more lanes so that we can utilize it.