Tuesday, July 28th 2026

Intel "Nova Lake-S" 12 Xe3P iGPU to Draw Up to 65 Watts

Intel's upcoming "Nova Lake-S" is gearing up for a launch later this year. However, rumors suggest that certain "Nova Lake-S" models with large integrated graphics might require significant power, increasing the TDP and peak power. According to the well-known Intel leaker Jaykihn on X, Intel's 16-core CPU SKU with 12 Xe3P cores will need specialized power delivery, with 65 W dedicated to integrated graphics. This SKU includes four P-Cores, eight E-Cores, and four LPE-Cores, along with 12 Xe3P GPU cores. This 4+8+8+12 core configuration is one of the few processors where integrated graphics require two VCCGT phases. In regular SKUs, VCCGT is a single-phase power rail for the integrated graphics inside the processor. However, since Intel aims to enhance its iGPU performance with "Nova Lake," a single phase is insufficient.

Previously, we learned that Intel's top-end, overclocking-focused, dual compute die "Nova Lake-S" CPU with 52 cores will feature a PL2 mode with a power level of 474 W. This also includes the possibility of three 8-pin CPU power connectors on high-end Z990 motherboards, an intriguing design choice considering that most enthusiast boards typically have two 8-pin EPS CPU connectors. The three 8-pin connectors are mainly intended for the highest-end overclocking designs, rather than being necessary for running the dual compute die designs. Motherboards with either two or three EPS connectors are still expected to support Intel's upcoming high-end 44-core and 52-core processors on the 175 W platform. However, we are likely to see various configurations, and motherboard designs are preparing for higher TDPs. Below image is illustration only.
Finally, we also know that the lower-end SKUs are expected to arrive first. Intel has SKUs coming with either one or two compute dies, featuring up to eight "Coyote Cove" P-Cores and 16 "Arctic Wolf" E-Cores, along with four LPE-Cores that are part of the I/O die. Depending on the SKU, Intel can include a single compute die for up to 28 cores total or two compute dies for a 52-core CPU SKU. It seems that the single compute die version will arrive first, with the dual compute die variants following. The 28-core "Nova Lake-S" DS version, a new SKU segment, is expected to launch in Q1 of 2027. For the regular overclocking-focused "K" SKUs, Intel reportedly plans an early Q2 launch between March and April.
Source: Jaykihn on X
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32 Comments on Intel "Nova Lake-S" 12 Xe3P iGPU to Draw Up to 65 Watts

#26
DavidC1
Why do you say 0%? You either have a source or don't if you are that confident. Even the manufacturer isn't 100% confident about timelines.
thestryker6Except that they do not do this. There have been zero dGPUs without Infinity Cache since RDNA 2 and there have been zero iGPUs with Infinity Cache other than Halo. It's a glaring hole in AMD's iGPU design that I thought they would address with RDNA 3.5, but instead they opted for more CUs.
Because any useful amount of cache would add quite a lot of die space.

Strix Point was supposed to have IC by the way. But it was replaced with the NPU block.
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#27
XeonsNOpterons
GeddagodConsidering the compute is the 4+8 tile, seems like the compute tile will be on N2.
Honestly I expect the "large" variant of the iGPU tile to be external more than I do the 4+8 tile though. Even if Intel can gain PPA by moving the 4+8 compute tile to N2P, it's so much volume that IFS is going to lose by not making it on 18A. Unlike the large iGPU tile which will be comparatively more niche. Plus, I expect the iGPU to gain more from the move to N2P than the compute tile might.
I am pretty sure by the latest leaks that Intel is making virturally all of Nova Lake's compute tiles on 18A, not TSMC. Their yields have dramatically improved apparently.
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#28
Geddagod
XeonsNOpteronsI am pretty sure by the latest leaks that Intel is making virturally all of Nova Lake's compute tiles on 18A, not TSMC.
By the latest "analyst report" sure. I wouldn't classify as what most investment firms pull up in their analyst reports as leaks either tbh lol.
By the same source that this article used, Jaykihn on twitter, like a week before that report came out, no, only the 4+0 compute tiles will be on 18A.
XeonsNOpteronsTheir yields have dramatically improved apparently.
That never really should have been a reason why, at the very least, the 4+8 compute tile wouldn't have been fabbed internally. That die would be, by all means, very small. Much smaller than even PTL, which was the lead 18A product. And PTL's 18A compute tile itself was also smaller than many flagship smartphone chip die sizes.
The problem is that you lose perf and power by not using N2P. Plus you would need to spend a sizable amount of money tooling the empty shells.
What's really interesting though is that AMD is rumored to be using N3 for most of their mainstream mobile lineup too for Zen 6, so why Intel would feel the need to use a more advanced leading edge node rather than their on par 18A-P stuff is kinda confusing.
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#29
XeonsNOpterons
GeddagodBy the latest "analyst report" sure. I wouldn't classify as what most investment firms pull up in their analyst reports as leaks either tbh lol.
By the same source that this article used, Jaykihn on twitter, like a week before that report came out, no, only the 4+0 compute tiles will be on 18A.
I do not really trust Jaykihn much, nor MLID.
GeddagodThat never really should have been a reason why, at the very least, the 4+8 compute tile wouldn't have been fabbed internally. That die would be, by all means, very small. Much smaller than even PTL, which was the lead 18A product. And PTL's 18A compute tile itself was also smaller than many flagship smartphone chip die sizes.
The problem is that you lose perf and power by not using N2P. Plus you would need to spend a sizable amount of money tooling the empty shells.
What's really interesting though is that AMD is rumored to be using N3 for most of their mainstream mobile lineup too for Zen 6, so why Intel would feel the need to use a more advanced leading edge node rather than their on par 18A-P stuff is kinda confusing.
18A from what I know has better performance per watt than N2s. Just lower density. And considering how underwhelming Zen 6 Venice's turbo clock speeds are, I doubt N2 even reaches its claims. I would eat a hat if Zen 6 desktop turbo clocks much past 6.2GHz out of the box.
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#30
Geddagod
XeonsNOpteronsI do not really trust Jaykihn much, nor MLID.
Both of them, even MLID, should have better track record than those financial analyst reports lol. And MLID's track record isn't especially good either.
Every single major "leaker" (MLID, Bionicsquash, Jaykihn, Raichu, etc etc) has at least the 8+16 tile as being external (which the analyst report that you cite also thinks got moved over to 18A).

Also mind you, I don't know why you would believe the report more, when by now it should be much too late to switch over compute tiles like how the report suggested. Even if we believe the 4+8 tile development could have been resurrected with only a minor delay, as we had rumors of 4+8 being on 18A-P too at one point, the 8+16 tiles switching over like the report suggests would have added a significant delay, as that was allegedly always supposed to be N2.
Sounds very ARL-esque, where only the 6+8 tile was once upon a time rumored to be internal (and we know Intel officially did claim they had a 20A compute tile in development that got canned) and the 8+16 tile was always supposed to be external lol.
XeonsNOpterons18A from what I know has better performance per watt than N2s.
From what we see in PTL, where the frequency/power curve is pretty much identical to N3B, 18A does not have better or even the same perf/watt as N2.
XeonsNOpteronsAnd considering how underwhelming Zen 6 Venice's turbo clock speeds are, I doubt N2 even reaches its claims. I would eat a hat if Zen 6 desktop turbo clocks much past 6.2GHz out of the box.
Remember, most Zen 4 server skus had no good Fmax gains over Zen 3 server either. And yet client saw a very good Fmax bump.
And Zen 5 server had most skus see a very nice bump in Fmax... and Zen 5 client was the only Zen DT generation afaik to see no Fmax bump.

And specifically for Fmax, that's where 18A looks the least impressive. Don't forget Panther Lake is a 300mhz regression in Fmax vs ARL-H. BSPD also brings thermal density challenges that could challenge Fmax in DT.
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#31
thestryker6
XeonsNOpteronsI do not really trust Jaykihn much, nor MLID.
Jaykihn has a very good track record and more importantly follows up when things change and cites preliminary for things with lower degree of certainty. It's also not particularly believable that Intel would switch NVL to internal because the TSMC capacity would have already been paid for and they would need to have something ready to be manufactured there in its place. 18A also has some inherent design choices which would likely limit desktop clock speeds. I suspect that if 18A-P was ready for volume we might have seen one of the desktop die using it. I wouldn't be particularly surprised if some of the NVL mobile die were internal though.
DavidC1Why do you say 0%? You either have a source or don't if you are that confident. Even the manufacturer isn't 100% confident about timelines.
That level of performance uplift would put RDNA 5 at a significant increase over RDNA 4 and Blackwell which is simply not happening. The rumors regarding the handheld APU indicate minimal CPU and low clock speeds on the GPU. It might be possible to match mobile PTL at half the power, but that would be due to overall efficiency gains and not just GPU performance. I imagine the G3 would stand up better in perf/W than fully enabled PTL.

As for the timeline there's a low chance of any console launching next year let alone a handheld which initial rumors pointed at being original MSRP Steam Deck priced. While they might get away with a $1000+ console the chances of a $750+ handheld console being viable is extremely low.
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#32
Geddagod
thestryker6I suspect that if 18A-P was ready for volume we might have seen one of the desktop die using it.
Intel has confirmed that 18A-P will be used in NVL. Though rumor is that it's only the iGPU tiles and SOC tiles on that node, other than the 4+0 tile.
18A-P does seem to have some improvements that will help in the Fmax department for sure though, and there is that rumored 8+0 bLLC desktop gaming 18A-P tile rumored to be coming out in 2027 that is based on NVL IP (though allegedly will launch with the RZL lineup).
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