MediaTek CEO Anticipates Q4 2025 Taping-out of First 2 nm Chip Design
As previously promised, Dr. Rick Tsai took to the Computex 2025 stage earlier today. The MediaTek CEO's keynote speech included a teaser for next-gen. Currently, the fabless chip design firm's best offerings are manufactured at TSMC foundries—utilizing 3 nm node processes. According to inside track knowledge, the forthcoming Dimensity 9500 mobile chipset will be based on "N3P." During today's important presentation, Tsai announced his company's next major leap—with "2 nm silicon innovation." According to a presentation slide, a tape-out phase is anticipated by this September. Industry experts reckon that a futuristic flagship—perhaps "Dimensity 9600"—SoC will benefit from this generational jump. Finalized products could arrive around late 2026; with MediaTek reportedly being on TSMC's 2 nm (N2) mass production order books. Officially, MediaTek's shift from 3 nm into 2 nm is expected to improve chip performance—with an estimated 15% uplift—while reducing power consumption (by ~25%).
