Frore Systems today announced LiquidJet Diamond, a new AI Factory liquid cooling coldplate featuring an integrated diamond spreader. The accelerating demand for AI Tokens, coupled with energy scarcity, is spurring hyperscalers to find new ways to increase the efficiency of AI Factories. LiquidJet Diamond Coldplate boosts AI Tokens/Watt and revenue by 35% compared to traditional skived coldplates, with the increased revenue flowing directly to profit.

LiquidJet Diamond builds on the previously announced Frore Systems LiquidJet coldplate. LiquidJet coldplate employs a unique 3D ultra short-loop multi-stage design which can be precisely customized to the power map of each GPU, including extreme hotspots. This precision is critical as GPUs grow in complexity and power draw to meet AI demand. LiquidJet delivers 12°C reduction in GPU die temperature which directly translates to 25% higher tokens/watt efficiency. LiquidJet Diamond adds an additional spreader with integrated diamond wafers to the coldplate bottom, positioned precisely at the hotspot locations. LiquidJet Diamond delivers an additional 10 °C reduction in hotspot die temperature, boosting increase in Tokens/Watt to 35%.

An MSI GeForce RTX 5080 16G Ventus 3X reportedly stopped working after its owner injected an unofficial version of DLSS 5 into a heavily modded copy of Grand Theft Auto 5. Reddit user "wax469" said the card had been running fine for about a month before the crash. According to the post, the screen began flashing uncontrollably about five minutes into a session, and the system refused to boot afterward. Swapping to his Ryzen 9 9950X3D2's integrated graphics let the PC start normally, and reinstalling the RTX 5080 brought the failure back. A replacement card of the same model has apparently worked without issues since.

It's worth being cautious here. NVIDIA has not released DLSS 5 for GTA 5, so the injection relied on unofficial tools, and the user says the card was running at stock settings with no overclock. There's no photo evidence of physical damage, and it's entirely possible a manufacturing defect was already present and just got exposed under load. Whether DLSS 5 had anything to do with it remains unconfirmed. The user was running a heavily modified version of GTA 5 Legacy, and adding unofficial DLSS 5 seems to be what eventually led to the failure.

A Ryzen 9 9950X3D has reportedly died just an hour after being moved into an ASUS ROG Crosshair X670E Hero motherboard. According to Reddit user SpecialistConcept423, posting in r/GamersNexus, the chip had been running fine for about a year and a half in an ASRock X670E Taichi Carrara before the swap. After switching to the new board, no manual overclocking or voltage tweaks were applied; only one of the board's built-in memory presets was enabled for a set of SK hynix 6200 MHz modules. After saving that setting and rebooting, the board threw a "00" Q-Code and refused to post. Pulling the CPU and inspecting it revealed two brown marks on its contacts, which all but confirmed the catastrophic failure.

Things got stranger when the user resorted to an older Ryzen 5 8500G that had previously worked fine on the same board. That chip apparently now throws a "4D" code too, pointing at the motherboard itself as the culprit, not just the CPU. There's no confirmation yet on whether a faulty BIOS, a bad batch of boards, or something else is to blame, and ASUS hasn't commented on this specific case. It is worth noting that the ASUS board was not new, and it had undergone USB-related repairs and a BIOS rewrite. The user has since contacted AMD in Brazil for an RMA, but has shared no updates yet.

NVIDIA appears to be preparing a new variant of the RTX 5070, this time built on the bigger GB203 die instead of the GB205 chip the card has shipped with since launch. The information comes from leaker hongxing2020, who also mentioned a new driver arriving on September 9, though it's not clear if that's tied to this specific SKU. This wouldn't be the first time NVIDIA has done this. The GeForce RTX 5060 normally runs on the GB206 die, but some retail units turned up with GB205 silicon instead, cut down to match the same specs. The jump to GB203 is a much bigger one for the RTX 5070, though. It's the same chip used in the RTX 5070 Ti and RTX 5080, measuring 378 mm² against the GB205's 263 mm².

To match the RTX 5070's 6,144 CUDA cores and 12 GB of GDDR7 on a 192-bit bus, NVIDIA would need to disable nearly 43% of the GB203's cores and shut off two of its eight memory channels. The likely explanation for this change is binning. GB203 dies that fall short of RTX 5070 Ti or RTX 5080 requirements probably still work fine at RTX 5070 specs, so NVIDIA gets to use them instead of scrapping them. There's no indication the GB203 variant will actually perform any better than the current GB205-based RTX 5070, since the specs are expected to stay the same either way. Board partners haven't said anything yet, so it's still worth treating this as a rumor until a retail card or driver listing actually confirms it.

According to Korean media, Samsung Foundry, a division that operates silicon manufacturing as a subsidiary of Samsung Electronics, is reportedly allocating significant capacity for HBM4 base die manufacturing. For HBM4, Samsung is producing the base die on a 4 nm node, which reportedly receives half of the entire manufacturing capacity of the 4 nm node, internally referred to as SF4. Customers of HBM4 and the upcoming HBM4E memory standards are now requesting base dies to be filled with custom logic. For instance, customers could implement custom logic like memory controllers and PHYs directly on the HBM base die, significantly reducing the area occupied by these components on the main compute chiplet.

Samsung operates its SF4 manufacturing at Pyeongtaek Campus 2 (P2) and Campus 3 (P3) on lines S5 and S6. An increase in manufacturing is not only coming for ASIC designs by external customers but also for HBM4 base die manufacturing, which is becoming especially important for ASIC customers aiming to maximize the performance of their designs.

Intel Foundry might win the contract to manufacture base dies for HBM4E memory from SK hynix, according to the South Korean Herald. Reportedly, SK hynix is considering diversifying its base die supplier from solely TSMC to a dual sourcing strategy involving both TSMC and Intel, with Intel Foundry potentially securing a significant portion of the contract. As readers may recall, HBM4E memory allows for the implementation of a base die with custom logic, with DRAM dies stacked on top. Until now, SK hynix has only considered TSMC for this application, but now Intel is also being considered.

For instance, customers could implement custom logic like memory controllers and PHYs directly on the HBM4E base die, significantly reducing the area occupied by these components on the main compute chiplet. SK hynix would send the design to Intel, which would then provide these base dies to SK hynix. The South Korean memory giant would subsequently stack DRAM on top. This approach would free up space on the main compute tile in any AI accelerator for more processing units, reduce latency, and significantly improve performance. However, the question remains as to which Intel node would be used. Up until HBM3E, SK hynix used its own nodes to manufacture base dies. However, as those are 10 nm class nodes, customers are now requiring something more advanced.

CEA-Leti today announced a major milestone in the evolution of 3D integration for high-performance computing (HPC), advanced smart-vision systems and artificial intelligence (AI), demonstrating a functional test vehicle utilizing die-to-wafer (D2W) hybrid bonding with pitches down to 1 μm. The findings were presented at the Electronic Components and Technology Conference (ECTC) 2026.

As Moore's Law reaches physical limits, the semiconductor industry is increasingly relying on 3D stacking to enhance performance and energy efficiency. This D2W technology addresses a critical bottleneck in AI accelerator design: interconnect density and bandwidth. By vertically stacking device layers with ultra-fine pitches, the technology shortens interconnect paths, significantly increasing data transfer speeds while reducing power consumption.

Samsung is reportedly planning to bring its 2 nm process to the base die of HBM4E, its 7th-generation high-bandwidth memory. This comes just a month after the company shipped the industry's first commercial HBM4, and alongside a separate effort to redesign the HBM4E power delivery network to handle the increase in power bumps from 13,682 to 14,457 within the same footprint. Until HBM3, the base die had a somewhat passive role, sitting at the bottom of an HBM stack and handling power and signal control. Starting with HBM4, it took on a more active role by handling some compute tasks directly, making the underlying process node increasingly important. For HBM4, Samsung already had an edge here, using 4 nm logic base dies from its own foundry paired with its latest 1c DRAM, well ahead of the 12 nm (N12) process SK hynix sources from TSMC. Moving to 2 nm for HBM4E would extend that lead further, improving power efficiency, thermal management, and area utilization.

The other key players in the industry are also focusing on custom HBM4E as the next battleground, with TSMC stating it plans to use its 3 nm process for custom HBM4E, and SK hynix also working on its own variant. With its latest 2 nm node push, Samsung appears to be making a deliberate move to stay a step ahead on process technology. Standard HBM4E is expected mid-year, with custom product tape-in following in the second half of the year. The Business Korea report also points to the foundry angle. Producing HBM base dies internally helps Samsung Foundry keep fab utilization high, and the 2 nm node is expected to play a major role in ramping production at the Taylor fab in Texas. There, equipment installation is already underway, with the first wafer tape-in targeted before year-end.

AMD Ryzen Threadripper Pro 9995WX HEDT processor with 96 cores and 192 threads comes with a default TDP of 350 W. However, heavy overclocking can bring the CPU to 1,300 W and requires a custom integrated heat spreader (IHS) that serves as a direct-die waterblock. In the latest endeavor by Geekerwan, the enthusiast created a custom fin structure inside the Ryzen Threadripper Pro 9995WX IHS that serves as a direct-die waterblock to achieve an impressive overclock of 5.325 GHz, drawing an astonishing 1,340 W during load, with the entire system drawing around 1,700 W. According to Geekerwan, he contacted ASUS China regional manager Tony Yu to experiment with different IHS designs before "ruining" the IHS of a $12,000 HEDT CPU. He then proceeded with trying a straight fin structure common in commercial waterblocks, but also conducted computer simulations that showed a curved, wavy S-shaped fin structure is the most efficient in capturing heat, as the coolant flows over a longer distance with minimal obstruction, resulting in 20% better cooling than the straight fin structure.

The IHS of the AMD Ryzen Threadripper Pro 9995WX processor is 4.1 mm thick, which left Geekerwan with about 2.0 mm of fin depth and about 2.1 mm for the structural integrity of the IHS, which is subject to a lot of water pressure. After a heavy 19-hour session of CNC milling, the result is a CPU that ran between 30-50°C, which is an amazing temperature under Cinebench 2026 load. The system also placed 7th in Cinebench R23, just behind an LN2-cooled AMD Ryzen Threadripper Pro 7995WX running at 6.2 GHz. Impressive heat dissipation and the massive 5.325 GHz clock on a 96-core system are also made possible with an industrial chiller, two Bosch water pumps from cars, and a 37-gallon water tank. You can check out the entire process below.

At last week's Open Innovation Platform Ecosystem Forum in Amsterdam, TSMC provided more details over its custom HBM for the HBM4 generation, according to reports from HardwareLUXX. The company's custom C-HBM4E logic die is expected to shift to the N3P node, alongside a voltage drop from 0.8 V to 0.75 V. According to TSMC's presentation, the move targets roughly 2× better power efficiency versus today's DRAM processes. Even standard HBM4 base dies will see upgrades. Instead of using a conventional DRAM process as in HBM3E, TSMC plans to manufacture HBM4 base dies on its N12 logic node, reducing operating voltage from 1.1 V to 0.8 V. The company expects this alone to provide around a 1.5× efficiency gain. For C-HBM4E specifically, the base die doesn't just move to the N3P node, it also integrates the memory controllers directly into the stack. Those blocks normally sit on the host SoC, so the PHY becomes a fully custom design as well.

Moreover, TSMC is expanding its advanced packaging lineup with updated InFO and SoW options, but CoWoS remains the company's main growth driver. After moving from 1.5× to 3.3× reticle sizes with support for eight HBM chips, CoWoS now heads toward CoWoS-L, enabling up to 12 HBM3E/HBM4 stacks for 2026 AI parts, followed by a larger A16 generation version planned for 2027. TSMC is also securing major customers for its custom HBM logic dies. Micron has selected the foundry to build the logic base die for its HBM4E parts, with volume production planned for 2027. SK Hynix is also reportedly preparing its first custom HBM4E products for the second half of next year. According to Korea Financial Times, SK Hynix will use TSMC's 12 nm process for mainstream server-grade HBM base dies, while NVIDIA's top-end GPUs and Google's TPUs will step up to a 3 nm node.

SK hynix appears to be expanding its DDR5 lineup with several new chips rated for a native 7200 MT/s speed above the current JEDEC 6400 MT/s standard. Listings spotted by @unikoshardware on Chinese retailer JD.com show new SK hynix DDR5 modules using part numbers not yet seen in the market. According to the findings, SK hynix has prepared four new dies, all capable of 7200 MT/s (denoted by the "KB" suffix), with densities ranging from 2 GB to 4 GB. These include the company's first 2 GB B-die and a 4 GB M-die, marking the first time this process node has been offered at that capacity.

Just last week, we reported on the second generation of SK hynix DDR5 memory chips with 3 GB A-die ICs where the sample reportedly uses an 8-layer PCB. As noted before, to fully exploit the new die's potential, manufacturers are expected to move to 10 or 12-layer PCBs for greater signal integrity, something that would come in handy especially when overclocked. These listings likely represent early samples, with improved designs expected once production ramps up. SK hynix hasn't officially announced the new chips yet, but the listings suggest development is well underway.

According to market reports, NVIDIA is planning to develop its own High Bandwidth Memory (HBM) Base Die design, with production targeting 3 nm process technology and trial manufacturing expected to begin in late 2027. TrendForce, citing Commercial Times, sees this as a strategic move that would allow NVIDIA to control the underlying logic components of HBM modules regardless of which memory manufacturer supplies the stacked memory layers. The news disrupted the HBM industry, where SK Hynix currently dominates. While SK Hynix uses primarily in-house Base Die solutions, it relies on advanced manufacturing processes from companies like TSMC to achieve speeds above 10 Gbps. Memory manufacturers typically lack the complex design capabilities needed for sophisticated Base Die and ASIC development.

NVIDIA's plan seems to aim at tightening its grip on its ecosystem through the NVLink Fusion platform giving customers more mix-and-match choices. However, cloud service providers might push back against NVIDIA's Base Die solutions, as many first went for ASIC development to cut their reliance on NVIDIA. At the same time, SK Hynix keeps pushing its HBM4 technology forward. The company just recently shipped 12-layer samples with 36 GB capacity and speed over 2 TB per second (60% faster than HBM3E). HBM4 is expected to deliver higher speeds and stacking with more complex packaging integration. As we previously reported, NVIDIA and AMD will deploy customized HBM4 memory in their upcoming AI accelerators. Combined with NVIDIA's plans to manufacture its own HBM Base Die and SK Hynix's accelerated HBM4 production timeline, the HBM market is about to enter a new phase of competition and change.

Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, announced the successful tape out of one of the industry's first UCIe IP subsystem on TSMC's N2 process, supporting 36G die-to-die data rates. The solution is fully integrated with TSMC's Chip-on-Wafer-on-Substrate (CoWoS ) advanced packaging technology, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.

This milestone builds on the recent release of the Alphawave Semi AI Platform, proving readiness to support the future of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads. With this tape-out, Alphawave Semi becomes one of the industry's first to enable UCIe connectivity on 2 nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.

AMD is preparing the next-generation mobile processor based on Zen 6 "Medusa Point" APUs. According to industry leaker HXL, the new lineup will feature a surprisingly high core count, especially on the top-end Ryzen 9 model, which is expected to pack 22 CPU cores. Under the hood, the Ryzen 5 and Ryzen 7 Medusa Point APUs will use a hybrid layout that combines four high-performance classic cores, four dense cores optimized for efficiency, and two ultra-low-power cores. On the graphics side, these chips will offer eight RDNA 3.5+ compute units, an upgrade from previous designs but still modest compared to some rivals. What really stands out is the Ryzen 9 variant, which reportedly adds a second Core Complex Die from AMD's desktop lineup. That extra 12-core CCD joins the main ten-core die, bringing the total to 22 cores. While this pushes the CPU core count, AMD keeps the integrated graphics configuration unchanged, with just eight compute units.

Initial performance data hints that this trimmed-down GPU might run about 20 to 25 percent slower than the 12-CU Radeon 890M used in earlier models. The eight CU GPU is half the power of current generation "Strix Point" with 16 CUs, but Medusa Point packs some RDNA 3.5+ upgrades. Even then, the raw CPU power should appeal to users who rely on heavily threaded applications, particularly in ultraportable laptops and mobile workstations. Medusa Point is built on the FP10 package, allowing for a slightly larger die size that houses the new core arrangement without sacrificing efficiency. Including dedicated low-power cores also marks AMD's first embrace of a heterogeneous x86 approach, similar to Intel's recent Core Ultra series. While more serious graphics work will mandate a combination of discrete GPUs for demanding workloads, Medusa Point will set new expectations for integrated CPU performance in thin, light notebooks.

Die shots of Intel's "Arrow Lake" desktop processors have appeared online, confirming the chiplet design we have known about since the launch. The images annotated by the YouTube channel HighYield show a four-tile arrangement mounted on a base die made with Intel's 22 nm FinFET process. The compute tile sits at the top left, built on TSMC's N3B node and covering 117.24 mm². To its right are the SoC tile on TSMC's N6 node measuring 86.65 mm², and the GPU tile, which houses four Xe cores alongside an Arc Alchemist render slice. The I/O tile, at 24.48 mm² on the same N6 node, completes the group at the bottom left. Intel has redesigned its hybrid core layout for Arrow Lake, moving away from separate P-core and E-core clusters. Four of the eight high-performance P-cores line the die's outer edges, with the remaining four in the center. In between these lie the four efficiency E-core clusters, each sharing 3 MB of L2 cache. A unified 36 MB L3 cache ring bus connects to every core, allowing E-cores to tap into that larger cache pool for the first time. Intel aims to spread heat more evenly and boost background task performance.

The I/O tile integrates Thunderbolt 4 controllers, PCIe buffers and PHYs. The SoC tile carries display engines, media accelerators and DDR5 memory controllers. All tiles are bonded to the base die via Intel's Foveros Omni stacking technology. Arrow Lake also reflects a shift in Intel's manufacturing strategy. Plans to use Intel's 20A node were dropped in favor of TSMC processes, making this the first desktop CPU from Intel that relies almost entirely on external foundries. On the software side, Intel has begun offering its IPO profiles in select prebuilt systems. These presets optimize CPU and memory settings for a hassle-free performance boost that remains within warranty limits. Meanwhile, the native 200S Boost overclocking option is rolling out via BIOS updates. Early tests suggest that 200S Boost alone yields modest gains unless paired with very high-speed DDR5 modules, while IPO profiles deliver more consistent improvements with mainstream memory configurations.

Surface defects on the GPU die of a PowerColor Radeon RX 9070 XT Hellhound have been linked to excessive thermal hotspots, according to analysis following Igor's Lab's investigation. Microscopic examination revealed 1,934 pits across the silicon die surface despite proper thermal interface material application. The defects affect over one percent of the chip's surface area, with the largest measuring 12.59 µm in depth and 212.36 µm in diameter—significantly exceeding industry tolerances. These imperfections impede heat transfer, causing localized temperatures to reach 113°C, exceeding the 110°C threshold for RDNA GPUs and triggering thermal throttling. The defects appear to stem from flaws in the backgrinding process that thins silicon wafers for packaging. Improper process control creates surface irregularities that compromise thermal conductivity and structural integrity.

The discovery raises questions about the effectiveness of automated optical inspection systems in detecting subtle surface abnormalities. TSMC, the maker of these chips, uses optical recognition tools to see if any defects occurred. AMD stated: "We are aware of the reported issue and believe this to be an isolated incident. We are working with our partners and internal teams to understand the issue." The company maintains this is an isolated case, though the findings suggest potential gaps in quality control protocols. Users experiencing thermal issues with affected RX 9070 XT units should initiate the RMA process for replacement while AMD and PowerColor investigate whether these defects exist beyond the identified sample. We hope no further issues are present, and so far, PowerColor hasn't received any customer complaints. We are on the lookout for further situation development. We reviewed PowerColor's Radeon RX 9070 Hellhound, and found no issues on our unit, so this indeed remains an isolated case so far.

Blue Cheetah Analog Design today announced the successful tape-outs of its next generation BlueLynx die-to-die (D2D) PHY on Samsung Foundry's SF4X 4 nm advanced manufacturing process. The latest PHY supports both advanced and standard chiplet packaging with an aggregate throughput exceeding 100 Tbps while achieving industry-leading silicon area footprint and power consumption. BlueLynx D2D subsystem IP enables chip architects to meet the bandwidth density and environmental robustness necessary to ensure production deployment success while preserving use case flexibility.

Using Samsung Foundry's SF4X 4 nm advanced process, the latest BlueLynx PHY supports both standard 2D and advanced 2.5D packages and enables system designers to seamlessly change packaging technologies in current and future implementations. Customer deliveries started in 2024 with silicon characterization in both advanced and standard packaging applications expected in early Q2 2025.

A few days ago, we published a report about Intel's 18A yields being at an abysmal 10%. This sparked quite a lot of discussion among the tech community, as well as responses from industry analysts and Intel's now ex-CEO Pat Gelsinger. Today, we are diving into known information about Intel's 18A node and checking out what the yields of possible products could be, using tools such as Die Yield Calculator from SemiAnalysis. First, we know that the defect rate of the 18A node is 0.4 defects per cm². This information is from August, and up-to-date defect rates could be much lower, especially since semiconductor nodes tend to evolve even when they are production-ready. To measure yields, manufacturers use various yield models based on the information they have, like the aforementioned 0.4 defect density. Expressed in defects per square centimeter (def/cm²), it measures manufacturing process quality by quantifying the average number of defects present in each unit area of a semiconductor wafer.

Measuring yields is a complex task. Manufacturers design some smaller chips for mobile and some bigger chips for HPC tasks. Thus, these two would have different yields, as bigger chips require more silicon area and are more prone to defects. Smaller mobile chips occupy less silicon area, and defects occurring on the wafer often yield more usable chips than wasted silicon. Stating that a node only yields x% of usable chips is only one side of the story, as the size of the test production chip is not known. For example, NVIDIA's H100 die is measuring at 814 mm²—a size that is pushing modern manufacturing to its limits. The size of a modern photomask, the actual pattern mask used in printing the design of a chip to silicon wafer, is only 858 mm² (26x33 mm). Thus, that is the limit before exceeding the mask and needing a redesign. At that size, nodes are yielding much less usable chips than something like a 100 mm² mobile chip, where defects don't wreak havoc on the yield curve.

Thermal Grizzly, a high-performance cooling solutions provider, unveils a new line-up of products specifically designed for Intel's LGA 1851 socket, the latest Intel Core Ultra 200 Arrow Lake CPUs. The product line consists of four new solutions tailored to the improvements of 15th generation CPUs, including a CPU contact frame, a direct die water block, a CPU delidding tool and a delidding heater. Today, three of these products are now officially launched and available for purchase on the Thermal Grizzly web shop and through its Partner Reseller Network.

Intel 1851 CPU Contact Frame V1
In addition to a new internal contour for the contact surface, the new Intel 1851 CPU Contact Frame V1 considers the position of the socket on the motherboard. The thermal hotspot has shifted with the Arrow Lake CPUs and is now located further north compared to its predecessor. With a slight shift of Socket 1851 compared to LGA1700, Intel has attempted to counter the hotspot shift. Thus, CPU coolers designed for Socket 1700 can also be used with Socket 1851. The shift in the socket makes previous contact frames for Socket 1700 incompatible with 1851, which is why Thermal Grizzly now offers the Intel 1851 Contact Frame V1.

Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today revealed the successful delivery of first silicon for its NuLink -2.0 PHY, manufactured in a 3 nm process. The device achieves 64 Gbps/bump, the industry's highest performance for a die-to-die PHY solution for multi-die architectures. While compatible with UCIe standard, the milestone further confirms Eliyan's ability to extend die-to-die connectivity by 2x higher bandwidth, on standard as well as advanced packaging, at unprecedented power, area, and latency.

The NuLink-2.0 is a multi-mode PHY solution that also supports UMI (Universal Memory Interconnect), a novel chiplet interconnect technology that improves Die-to-Memory bandwidth efficiency by more than 2x. UMI leverages a dynamic bidirectional PHY whose specifications are currently being finalized with the Open Compute Project (OCP) as BoW 2.1.

Based on information shared by a Baidu user called Piglin, we now have access to an annotated die image of Qualcomm's Snapdragon X Elite processor. This analysis provides insights into the architecture of this new system-on-chip, highlighting several key features, including large CPU cores, a GPU, and a complex cache system. The report indicates that the Snapdragon X Elite die measures 169.6 mm² and is fabricated using TSMC's N4P 4 nm-class process. A notable aspect of the die shot is the considerable size of the "Phoenix" Oryon CPU cores, each reportedly measuring around 2.55 mm². These cores are significantly larger than typical Arm CPU cores, which is logical given their original purpose for the data center. The SoC features a total of 12 CPU cores in an 8+4 configuration.

The GPU, called Adreno X1, takes up 24.3 mm² of die area, roughly half the size of the CPU and CPU cache section. Despite its compact size, Qualcomm claims the GPU delivers approximately 4.6 FP32 TFLOPS of raw performance. Interestingly, the 45 TOPS NPU, which Qualcomm has emphasized as a key feature, is not clearly visible in the image. Another significant aspect is the extensive cache system. The three quad-core CPU clusters each occupy 16.1 mm², and feature 12 MB of high-speed L2 cache. Additionally, 6 MB is dedicated to system-level cache on 5.09 mm² area, along with a separate GPU cache. In total, the CPU boasts 54 MB of caches distributed across the die. The report also compares the Snapdragon X Elite to Apple's M4 SoC. However, it's worth noting that this isn't an exact comparison, as Apple utilizes an N3E 3 nm-class node for its chip. Below is the annotated die of Snapdragon X Elite and Apple's M4 from the original report.

EK, the leading computer cooling solutions provider, is rolling out a brand-new water block built from the ground up for the LGA 1700 socket, explicitly designed for delidded Intel Core CPUs. It bears improvements that benefit 14th-generation CPUs and shares almost no parts with the previously released Intel Direct Die water block. It includes a purpose-developed cold plate, cooling fin structure, and mounting mechanism. It relies on standoffs positioned at the four corners of the water block to ensure optimal contact with the CPU, eliminating concerns about applying too much or too little pressure on the bare CPU die, just like the AM5 Direct Die water block. EK's latest water block features EK-Matrix7 compatibility, meaning the product's height and port distance are managed in 7 mm increments for easier loop planning and precise results.

EK-Quantum Velocity² Direct Die D-RGB - 1700 Core Edition
This new direct die LGA 1700 water block is built from scratch and made to squeeze every bit of performance out of the 14th-generation Intel Core CPUs. The top is seethrough glass-like acrylic, with rich D-RGB illumination behind the window, which is riddled with aluminium bars going over the top and two G1/4" extenders that interrupt the flow of the black-anodized aluminium bars. These G1/4" extenders are standard Torque micro extenders. They can be replaced by other products from the EK-Quantum Torque Micro series, be it extenders of different finish, HDP or HDC fittings.

Ahead of the 2024 Optical Fiber Communication Conference (OFC), MediaTek (last week) announced it is launching a next-generation custom ASIC design platform that includes the heterogeneous integration of both high-speed electrical and optical I/Os in the same ASIC implementation. MediaTek will be demonstrating a serviceable socketed implementation that combines 8x800G electrical links and 8x800G optical links for a more flexible deployment. It integrates both MediaTek's in-house SerDes for electrical I/O as well as co-packaged Odin optical engines from Ranovus for optical I/O. Leveraging the heterogeneous solution that includes both 112G LR SerDes and optical modules, this CPO demonstration delivers reduced board space and device costs, boosts bandwidth density, and lowers system power by up to 50% compared to existing solutions.

Additionally, Ranovus' Odin optical engine has the option to provide either internal or external laser optical modules to better align with practical usage scenarios. MediaTek's ASIC experience and capabilities in the 3 nm advanced process, 2.5D and 3D advanced packaging, thermal management, and reliability, combined with optical experience, makes it possible for customers to access the latest technology for high-performance computing (HPC), AI/ML and data center networking.

According to sources close to Seoul Economy, and reported by DigiTimes, Intel has reportedly chosen Samsung as a supplier for its next-generation Lunar Lake processors, set to debut later this year. The report notes that Samsung will provide LPDDR5X memory devices for integration into Intel's processors. This collaboration could be a substantial win for Samsung, given Intel's projection to distribute millions of Lunar Lake CPUs in the coming years. However, it's important to note that this information is based on a leak and has not been officially confirmed. Designed for ultra-portable laptops, the Lunar Lake-MX platform is expected to feature 16 GB or 32 GB of LPDDR5X-8533 memory directly on the processor package. This on-package memory approach aims to minimize the platform's physical size while enhancing performance over traditional memory configurations. With Lunar Lake's exclusive support for on-package memory, Samsung's LPDDR5X-8533 products could significantly boost sales.

While Samsung is currently in the spotlight, it remains unclear if it will be the sole LPDDR5X memory provider for Lunar Lake. Intel's strategy involves selling processors with pre-validated memory, leaving the door open for potential validation of similar memory products from competitors like Micron and SK Hynix. Thanks to a new microarchitecture, Intel has promoted its Lunar Lake processors as a revolutionary leap in performance-per-watt efficiency. The processors are expected to utilize a multi-chipset design with Foveros technology, combining CPU and GPU chipsets, a system-on-chip tile, and dual memory packages. The CPU component is anticipated to include up to eight cores, a mix of four high-performance Lion Cove and four energy-efficient Skymont cores, alongside advanced graphics, cache, and AI acceleration capabilities. Apple's use of on-package memory in its M-series chips has set a precedent in the industry, and with Intel's Lunar Lake MX, this trend could extend across the thin-and-light laptop market. However, systems requiring more flexibility in terms of configuration, repair, and upgrades will likely continue to employ standard memory solutions like SODIMMs and/or the new CAMM2 modules that offer a balance of high performance and energy efficiency.

The PC master race has yielded many interesting activities for enthusiasts alike, with perhaps the pinnacle of activities being overclocking. Usually, subjects for overclocking include CPUs, GPUs, and RAM, with other components not actually being capable of overclocking. However, the enthusiast force never seems to settle, and today, we have proof of overclocking an off-the-shelf 2.5-inch SATA III NAND Flash SSD thanks to Gabriel Ferraz, a Computer Engineering graduate, and TechPowerUp's SSD database maintainer. He uses the RZX Pro 256 GB SSD in the video, a generic NAND Flash drive. The RZX Pro uses the Silicon Motion SM2259XT2 single-core, 32-bit ARC CPU running up to 550 MHz. It has two channels at 400 MHz, each with eight chip enable interconnects, allowing up to 16 NAND Flash dies to operate. The SSD doesn't feature a DRAM cache or support a host memory buffer. It has only one NAND Flash memory chip from Kioxia, uses BiCS FLASH 4 architecture, has 96 layers, and has 256 GB capacity.

While this NAND Flash die is rated for up to 400 MHz or 800 MT/s, it only ran at less than half the speed at 193.75 MHz or 387.5 MT/s at default settings. Gabriel acquired a SATA III to USB 3.0 adapter with a JMS578 bridge chip to perform the overclock. This adapter allows hot swapping of SSDs without the need to turn off the PC. He shorted two terminals in the drive's PCB to get the SSD to operate without its default safe mode. Mass Production Tools (MPTools), which OEMs use to flash SSDs, were used to change the firmware settings. Each NAND Flash architecture has its own special version of MPTools. The software directly shows control of the Flash clock, CPU clock, and output driving. However, additional tweaks like Flash IO driving with subdivisions need modifications. Control and Flash On-Die Termination (ODT) and Schmitt window trigger (referring to the Schmitt trigger comparator circuit) also needed a few modifications to make it work.