AMD looks set to bring in more quarterly revenue than Intel for what appears to be the first time ever. Alongside its record Q3 2026 results, AMD guided Q4 revenue to approximately $17 billion, plus or minus 3%, or roughly $16.5 billion to $17.5 billion. Intel, on the other hand, expects Q4 revenue between $15 billion and $16 billion. Even the bottom of AMD's range sits above the top of Intel's, so unless either company misses its guidance badly, the flip is pretty much locked in.

Most of AMD's growth comes from the data center. AMD's Data Center segment hit a record $8.5 billion in Q3, up 97% year over year, on strong EPYC demand and the launch of the Instinct MI450 Series GPUs inside its Helios racks. AMD expects the segment to grow about 50% sequentially in Q4, while Client and Gaming is expected to drop by more than 20%. Intel's Q4 outlook, meanwhile, came in well below expectations, partly due to a two-week shutdown at Fab 28 in Israel that Intel says will cost about $300 million in Q4 revenue.

AMD and Anthropic today announced a strategic partnership to deploy up to 2 gigawatts of AMD Instinct MI450 Series GPUs in AMD Helios rackscale solutions, with deployment of the first gigawatt beginning in the first half of 2027. The extraordinary pace of AI adoption is driving rapid growth in demand for training and inference capacity. Anthropic is scaling its compute infrastructure to serve strong and growing demand for Claude, and its adoption of AMD Helios at gigawatt scale represents a major expansion of AMD's position at the center of the global AI infrastructure buildout.

Anthropic will deploy AMD Helios rackscale solutions featuring AMD Instinct MI455X GPUs, part of the AMD Instinct MI450 Series, together with AMD EPYC "Venice" CPUs, AMD Pensando networking and AMD ROCm software. Purpose-built for next-generation AI training and inference, Helios delivers the performance, efficiency and scale required for the most demanding AI workloads. This deployment builds on Anthropic's existing use of AMD Instinct MI355X GPUs.

AMD, a leader in high-performance and AI computing, and Celestica Inc., a global leader in data center infrastructure and advanced technology solutions, today announced a strategic collaboration to bring the new "Helios" rack-scale AI platform to market. The collaboration pairs AMD computing leadership with Celestica's expertise in delivering leading-edge networking switch technologies. At launch, Celestica will undertake the R&D, design and manufacturing of scale-up networking switches in the AMD "Helios" rack-scale AI architecture, based on the Open Compute Project (OCP), Open-Rack-Wide (ORW) form-factor.

The scale-up switches will utilize advanced networking silicon to enable the high-speed interconnect of the next-generation AMD Instinct MI450 Series GPUs, enabling leading-edge computing, optimized for large-scale AI clusters. Consistent with the open standards-based design of the "Helios" platform, the networking switches will utilize the Ultra Accelerator Link over Ethernet (UALoE) architecture for scale-up connectivity. AMD "Helios" will be available to customers in late 2026.

AMD and Meta today announced a 6-gigawatt agreement to power Meta's next generation of AI infrastructure across multiple generations of AMD Instinct GPUs. This agreement expands on the companies' existing strategic partnership and aligns roadmaps across silicon, systems and software to deliver AI platforms purpose-built for Meta's workloads. The first deployment will use a custom AMD Instinct GPU based on the MI450 architecture to deliver AI platforms that are optimized for Meta's workloads at gigawatt-scale. Shipments supporting the first gigawatt deployment are scheduled to begin in the second half of 2026 powered by the custom AMD Instinct MI450-based GPU and 6th Gen AMD EPYC CPUs, codenamed "Venice," running ROCm software and built on the AMD Helios rack-scale architecture. AMD Helios was developed jointly by AMD and Meta through the Open Compute Project to enable scalable, rack-level AI infrastructure.

"We are proud to expand our strategic partnership with Meta as they push the boundaries of AI at unprecedented scale," said Dr. Lisa Su, chair and CEO, AMD. "This multi-year, multi-generation collaboration across Instinct GPUs, EPYC CPUs and rack-scale AI systems aligns our roadmaps to deliver high-performance, energy-efficient infrastructure optimized for Meta's workloads, accelerating one of the industry's largest AI deployments and placing AMD at the center of the global AI buildout."

Vultr, the world's largest privately-held cloud infrastructure company, today announced a major milestone in its long-standing strategic collaboration with AMD (NASDAQ: AMD) to advance and scale AI workloads worldwide. Vultr will launch an AI supercluster, powered by AMD Instinct MI355X GPUs deployed in its new Springfield, Ohio cloud data center location. This 50 MW expansion delivers unprecedented performance per dollar for AI training and inference.

Vultr was among the first cloud providers to deploy AMD Instinct MI325X and AMD Instinct MI355X GPUs, and is now expanding its AI infrastructure with an additional 24,000 AMD Instinct MI355X GPUs in its new Springfield, Ohio campus. This significant deployment reinforces the collaboration between AMD and Vultr to deliver high-performance, energy-efficient AI infrastructure for customers worldwide. Looking ahead, Vultr will extend its adoption of AMD Instinct GPUs by integrating the next generation AMD Instinct MI450 series GPUs and the "Helios" rack-scale infrastructure, further advancing its commitment to the AMD AI platform roadmap.

AMD, Cisco and HUMAIN, a PIF company delivering global full-stack AI solutions, announced today plans to establish a joint venture aimed to support the development of Saudi Arabia's position as a leading provider of world-class AI solutions for regional and global customers. AMD, Cisco and HUMAIN will serve as founding investors in the joint venture, which is expected to begin operations in 2026 with plans to combine HUMAIN's state-of-the-art data centers with AMD and Cisco technology, delivering modern data center capacity with efficient power and lower capital expenditures. AMD and Cisco will act as exclusive technology partners to the joint venture, contributing their portfolio of products and services to its development of up to 1 GW of AI infrastructure by 2030.

The companies also announced the first phase of the project as a buildout of 100 MW AI infrastructure, with the intent to include HUMAIN modern data center capacity, AMD Instinct MI450 Series GPUs and Cisco's industry-leading critical infrastructure.

AMD (NASDAQ:AMD) today announced financial results for the third quarter of 2025. Third quarter revenue was a record $9.2 billion, gross margin was 52%, operating income was $1.3 billion, net income was $1.2 billion and diluted earnings per share was $0.75. On a non-GAAP basis, gross margin was 54%, operating income was $2.2 billion, net income was $2 billion and diluted earnings per share was $1.20. Our third quarter results did not include any revenue from shipments of AMD Instinct MI308 GPU products to China.

"We delivered an outstanding quarter, with record revenue and profitability reflecting broad based demand for our high-performance EPYC and Ryzen processors and Instinct AI accelerators," said Dr. Lisa Su, AMD chair and CEO. "Our record third quarter performance and strong fourth quarter guidance marks a clear step up in our growth trajectory as our expanding compute franchise and rapidly scaling data center AI business drive significant revenue and earnings growth."

AMD and Oracle have expanded their ongoing partnership aiming to grow AI infrastructure through big GPU clusters on Oracle Cloud Infrastructure (OCI). OCI will host the first AI supercluster available to the public that runs on AMD Instinct MI450 Series GPUs. The plan is to start with 50,000 units in Q3 2026 and expand further in 2027. The new systems will build on Oracle's existing AMD-based offerings, including Instinct MI300X and MI355X GPU instances, and introduce AMD's next-generation "Helios" rack design. Each rack combines Instinct MI450 GPUs, EPYC "Venice" CPUs, and Pensando "Vulcano" DPUs using liquid-cooled setups to boost performance while reducing costs.

AMD's upcoming MI450 accelerators series boasts up to 432 GB of HBM4 memory and 20 TB/s of bandwidth for each GPU. This allows for the training of much bigger AI models in-memory while AMD's UALink and UALoE interconnect standards make it possible for GPUs to communicate with hardware coherence. This cuts down on latency and CPU routing. Each GPU can also team up with up to three 800 Gbps Pensando "Vulcano" AI-NICs. These support advanced RoCE and UEC networking standards to enable high-throughput distributed training. AMD EPYC "Venice" CPUs with features for confidential computing and AMD's ROCm open-source software stack will complement the new units.

In an interview with Yahoo Finance right after the surprising OpenAI partnership announcement, AMD CEO Lisa Su confirmed that the next generation of Instinct MI450 graphics accelerators will use 2 nm process technology. "We are very excited about our MI450 generation. It has 2 nm technology, the most advanced fabrication capability," AMD CEO Lisa Su said. AMD uses TSMC's capabilities and technology, having been a loyal partner of the Taiwanese company for years. More details recently leaked from Kepler_L2 show that the TSMC N2P (2 nm) node is only used for the XCD (Accelerator Core Die), while the AID (Active Interposer Die) and MID (Media Interface Die) use the TSMC N3P process.

MI450 is set to go head-to-head with NVIDIA's Rubin generation, which uses the TSMC 3 nm (N3P) process. AMD said MI450 will deliver similar FP4/FP8 performance but with 1.5x more memory and bandwidth. AMD will use the TSMC 2 nm node for both Instinct MI450 and the next-generation EPYC "Venice" server processors, with the accelerators expected to be larger and much more complex to make. As we reported earlier, credible rumors suggest AMD will use Samsung HBM4 memory chips for the Instinct MI450 accelerators—though AMD hasn't confirmed this yet. With the year ending and CES 2026 just three months away, AMD is expected to showcase the next-gen Instinct MI400 series (and possibly even the new EPYC "Venice" generation) in January.

Samsung is reportedly set to be the main supplier of HBM4 memory to AMD's upcoming MI450 chips according to TrendForce citing SeDaily. The rumors (news) came just days after AMD announced a multi-year deal with OpenAI paving the way for a 6-Gigawatt partnership (and the option for OpenAI to acquire up to 10% of AMD). Collaboration between Samsung and AMD is nothing new as current generation chips such as MI350X and MI355X feature 12-high HBM3e memory from Samsung and Micron.

OpenAI made initial agreements with Samsung and SK hynix to obtain memory for its huge Stargate data center project last week, before joining forces with AMD. Reuters reports that OpenAI's needs might soar to 900,000 DRAM wafers - a number that could make up almost 40% of the world's total DRAM production. Maeil Business Newspaper states that Samsung plans to provide not just HBM but also graphics DRAM (GDDR) high-capacity SSDs, and LPDDR5X-PIM - low-power DRAM with in-memory computing - to use in AI applications for OpenAI's Stargate project. The industry seems to polarize even more around NVIDIA and AMD since Intel just teamed up with Team Green. To counter NVIDIA's proprietary NVLink, AMD is pushing for the Ultra Accelerator Link (UALink) open-standard alternative. This initiative managed to gather quite a sizable momentum, gathering partners such as Apple, Google, Microsoft, Synopsis, Meta, and Intel. The latter's presence in the UALink consortium remains to be seen, due to its latest partnership with NVIDIA.

AMD (NASDAQ: AMD) and OpenAI today announced a 6 gigawatt agreement to power OpenAI's next-generation AI infrastructure across multiple generations of AMD Instinct GPUs. The first 1 gigawatt deployment of AMD Instinct MI450 GPUs is set to begin in the second half of 2026. AMD's strong leadership in high-performance computing systems and OpenAI's pioneering research and advancements in generative AI places the two companies at the forefront of this important and pivotal time for AI.

Under this definitive agreement, OpenAI will work with AMD as a core strategic compute partner to drive large-scale deployments of AMD technology starting with the AMD Instinct MI450 series and rack-scale AI solutions and extending to future generations. By sharing technical expertise to optimize their product roadmaps, AMD and OpenAI are deepening their multi-generational hardware and software collaboration that began with the MI300X and continued with the MI350X series. This partnership creates a true win-win for both companies, enabling very large-scale AI deployments and advancing the entire ecosystem.

While AMD hasn't launched its upcoming Instinct MI400 series of accelerators yet, the company has started preparing its supply chain for what comes after. Thanks to SemiAnalysis, we have a clearer picture of what AMD's Instinct MI500 UAL256 rack will look like. At the base of each compute node, there will be a single "Verano" CPU paired with four Instinct MI500 accelerators. With up to 64 nodes, split across two 32-node racks, AMD plans to enable 256 logical GPUs and 64 CPUs per mega pod, working in tandem for advanced AI and HPC workloads. Instinct MI500s UAL256 will be AMD's second-generation rack-scale system, following the upcoming Instinct MI450X IF128 aka "Helios", scheduled for the second half of 2026. The Instinct MI500 UAL256 scale-up mega pod is scheduled to arrive in 2027, just in time for Verano and Instinct MI500 accelerator.

The Instinct MI500 UAL256 scale-up mega pod splits the compute into two 32-rack cabinets, with a single central rack connecting them and hosting 18 switching trays for networking. Each of these networking trays contains four 102.4T "Vulcano" switch ASICs, designed for 800G external throughput, and manufactured on TSMC's 3 nm node. For the central processor, AMD showed few details at its Advancing AI event, which claimed that Verano introduces the "Zen 7" microarchitecture for even higher IPC and support for even newer instruction sets. For now, it's not clear if AMD will increase CPU core counts beyond the up to 256 cores per package of "Venice." Still, we're hearing that Verano will retain the Socket SP7 infrastructure, which means it will likely retain the memory and PCIe interfaces introduced in 2026, such as PCIe Gen 6, UALink, and Ultra Ethernet.

At its "Advancing AI 2025" event, AMD rolled out its new Instinct MI350 lineup on the CDNA 4 architecture and teased the upcoming UDNA-based AI accelerator. True to its roughly one-year refresh rhythm, the company confirmed that the Instinct MI400 series will land in early 2026, showcasing a huge leap in memory, interconnect bandwidth, and raw compute power. Each MI400 card features twelve HBM4 stacks, providing a whopping 432 GB of on-package memory and pushing nearly 19.6 TB/s of memory bandwidth. Those early HBM4 modules deliver approximately 1.6 TB/s each, just shy of the 2 TB/s mark. On the compute front, AMD pegs the MI400 at 20 PetaFLOPS of FP8 throughput and 40 PetaFLOPS of FP4, doubling the sparse-matrix performance of today's MI355X cards. But the real game-changer is how AMD is scaling those GPUs. Until now, you could connect up to eight cards via Infinity Fabric, and anything beyond that had to go over Ethernet.

The MI400's upgraded fabric link now offers 300 GB/s, nearly twice the speed of the MI350 series, allowing you to build full-rack clusters without relying on slower networks. That upgrade paves the way for "Helios," AMD's fully integrated AI rack solution. It combines upcoming EPYC "Venice" CPUs with MI400 GPUs and trim-to-fit networking gear, offering a turnkey setup for data center operators. AMD didn't shy away from comparisons, either. A Helios rack with 72 MI400 cards delivers approximately 3.1 ExaFLOPS of tensor performance and 31 TB of HBM4 memory. NVIDIA's Vera Rubin system, slated to feature 72 GPUs and 288 GB of memory each, is expected to achieve around 3.6 ExaFLOPS, with AMD's capabilities surpassing it in both bandwidth and capacity. And if that's not enough, whispers of a beefed-up MI450X IF128 system are already swirling. Due in late 2026, it would directly link 128 GPUs with Infinity Fabric at 1.8 TB/s bidirectional per device, unlocking truly massive rack-scale AI clusters.

According to SemiAnalysis, AMD has planned its first-ever rack-scale GPU cluster for the second half of 2026, when it shows its first rack-scale accelerator, the Instinct MI450X IF128. Built on what's expected to be a 3 nm-class TSMC process and packaged with CoWoS-L, each MI450X IF128 card will include at least 288 GB of HBM4 memory. That memory will sustain up to 18 TB/s of bandwidth, driving around 50 PetaFLOPS of FP4 compute while drawing between 1.6 and 2.0 kW of power. In our recent article, we outlined that AMD split the Instinct MI400 series into HPC-first MI430X and MI450X for AI. Now for AI-focused MI450X, the company created both an "IF64" backplane for simpler single-rack installs and the full-blown "IF128" for maximum density. The IF128 version links 128 GPUs over an Ethernet-based Infinity Fabric network and uses UALink instead of PCIe to connect each GPU to three built-in Pensando 800 GbE NICs. That design delivers about 1.8 TB/s of unidirectional bandwidth per GPU and a total of 2,304 TB/s across the rack.

With 128 GPUs each offering 50 PetaFLOPS of FP4 compute and 288 GB of HBM4 memory, the MI450X IF128 system delivers a combined 6,400 PetaFLOPS and 36.9 TB of high-bandwidth memory, and MI450X IF64 provides about half of that. Since AI deployments require massive density of rack systems, AMD plans to possibly outnumber NVIDIA's upcoming system known as "Vera Rubin" VR200 NVL144 (144 compute dies, 72 GPUs), which tops out at 3,600 PetaFLOPS and 936 TB/s of memory bandwidth—about half of what AMD's IF128 approach promises. AMD will have a possibly more powerful system architecture than NVIDIA until the launch of VR300 "Ultra" NVL576, which has 144 GPUs, each carrying four compute dies, totaling 576 compute chiplets.

AMD is gearing up to expand its Instinct MI family in the latter half of 2026 with two purpose-built UDNA-based accelerators. These new models, MI430X UL4 and MI450X, will cater respectively to high-precision HPC tasks and large-scale AI workloads. The MI430X UL4 is designed for applications that rely heavily on double-precision FP64 floating-point performance, such as scientific simulations, climate modeling, and others. It features a large array of FP64 tensor cores, ensuring consistent throughput for tightly coupled compute jobs. Because a dedicated UALink switch from partners like Astera Labs or Broadcom won't be available at launch, AMD has chosen a four-GPU point-to-point mesh configuration for the MI430X UL4. This limited scale-up approach keeps latency low and synchronization tight, making it ideal for small cluster deployments. On the AI side, the MI450X embraces Ethernet-based Ultra Ethernet for scale-out.

With UEC-ready switches already on the market, this open-standard networking solution lets users build expansive AI farms across dozens or even hundreds of nodes. By relying on established Ethernet technology instead of the new UALink ecosystem, AMD provides customers with immediate, hardware-accelerated networking for both inference and training. While UALink promises an open, vendor-neutral accelerator-to-accelerator fabric, its progress has been slow. Committee reviews and limited investment in switch silicon have delayed switch availability. Broadcom, viewed as the primary UALink switch supplier, has been cautious about its commitment, given expected lower volumes compared to Ethernet alternatives. AMD's acceleration segmentation addresses these realities. The MI430X UL4 delivers high-precision compute in compact GPU meshes. The MI450X offers large-scale AI connectivity via Ethernet. Should UALink switch development catch up in the future, AMD could revisit native GPU-to-GPU fabrics.

At this year's Technology Symposium, TSMC unveiled an engaging multi-year roadmap for its packaging technologies. TSMC's strategy splits into two main categories: Advanced Packaging and System-on-Wafer. Back in 2016, CoWoS-S debuted with four HBM stacks paired to N16 compute dies on a 1.5× reticle-limited interposer, which was an impressive feat at the time. Fast forward to 2025, and CoWoS-S now routinely supports eight HBM chips alongside N5 and N4 compute tiles within a 3.3× reticle budget. Its successor, CoWoS-R, increases interconnect bandwidth and brings N3-node compatibility without changing that reticle constraint. Looking toward 2027, TSMC will launch CoWoS-L. First up are large N3-node chiplets, followed by N2-node tiles, multiple I/O dies, and up to a dozen HBM3E or HBM4 stacks—all housed within a 5.5× reticle ceiling. It's hard to believe that eight HBM stacks once sounded ambitious—now they're just the starting point for next-gen AI accelerators inspired by AMD's Instinct MI450X and NVIDIA's Vera Rubin.

Integrated Fan-Out, or InFO, adds another dimension with flexible 3D assemblies. The original InFO bridge is already powering AMD's Instinct cards. Later this year, InFO-POP (package-on-package) and InFO-2.5D arrive, promising even denser chip stacking and unlocking new scaling potential on a single package, away from the 2D and 2.5D packaging we were used to, going into the third dimension. On the wafer scale, TSMC's System-on-Wafer lineup—SoW-P and SoW-X—has grown from specialized AI engines into a comprehensive roadmap mirroring logic-node progress. This year marks the first SoIC stacks from N3 to N4, with each tile up to 830 mm² and no hard limit on top-die size. That trajectory points to massive, ultra-dense packages, which is exactly what HPC and AI data centers will demand in the coming years.

AMD is reported to be forming plans for its Instinct MI400 Accelerator series, according to a leaked internal email. This information was shared by a hardware tipster (HXL/@9550Pro) on Twitter, but their post has been deleted as some point today. Wccftech was quick enough to note down the details, and their report suggests that AMD is already making plans for an APU range that is set to succeed the unreleased Instinct MI300 lineup (expected later in 2023). Instinct MI400 accelerators are touted to drive next generation data center and cloud platforms.

The leaked email email contained information about three upcoming products: Weisshorn, MI450 and XSwitch. Kepler's recent tweet posits that Weisshorn is AMD's in-house moniker for Zen 6 "Morpheus" architecture-based Venice CPUs - these are alleged to form part of an upcoming EPYC lineup (slated for 2025 or 2026). Hardware experts reckon that AMD will introduce a new interconnect fabric with the MI400 series - "XSwitch" is speculated to be the company's main technological answer to NVIDIA's NVLINK.