Thursday, August 28th 2025
AMD Prepares EPYC "Venice" Platform to Break the 1,000 W Power Barrier
The kilowatt era of CPUs is upon us, as AMD is preparing specialized cooling for its next-generation SP7 socket powering EPYC "Venice". During the OCP APAC 2025 Summit in early August, Microloops held a presentation dedicated entirely to system-level cooling using custom high-performance cold plates, cooling distribution units, and much more. However, an interesting tidbit is the mention of AMD and its plan to likely cool CPUs with TDPs ranging from 700 to 1400 W. This marks AMD's first step into a kilowatt-level chip design, requiring kilowatt-level cooling. AMD is preparing to roll out its Zen 6 microarchitecture in 2026, with a server-focused flagship called EPYC "Venice." The new platform is expected to significantly increase core counts, utilizing full-sized Zen 6 cores and an updated I/O subsystem to target much stronger multithreaded throughput. AMD is reportedly configuring Venice to support as many as 256 CPU cores in a single package, a big leap intended to sharpen its position in dense compute environments.
Under the hood, Zen 6 CCDs are planned for TSMC's 2 nm N2 node, while the server I/O die will bring next-generation connectivity with PCIe Gen 6, doubling raw device bandwidth for GPUs, NVMe storage, and high-speed NICs. AMD has also pointed to memory bandwidth claims of up to roughly 1.6 TB/s, which could be achieved through faster DRAM clocks, expanding the memory controller to a 16-channel DDR5 layout from the current 12 channels, or supporting multichannel DIMM formats such as MR-DIMM and MCR-DIMM. Taken together, AMD says Venice will deliver approximately a 70% improvement in multithreaded performance compared to the current EPYC "Turin" family. However, all of that is shaping up to come with a significant power cost, as AMD gears up to cool these chips through customized solutions.
Sources:
AMD Presentation, via HXL
Under the hood, Zen 6 CCDs are planned for TSMC's 2 nm N2 node, while the server I/O die will bring next-generation connectivity with PCIe Gen 6, doubling raw device bandwidth for GPUs, NVMe storage, and high-speed NICs. AMD has also pointed to memory bandwidth claims of up to roughly 1.6 TB/s, which could be achieved through faster DRAM clocks, expanding the memory controller to a 16-channel DDR5 layout from the current 12 channels, or supporting multichannel DIMM formats such as MR-DIMM and MCR-DIMM. Taken together, AMD says Venice will deliver approximately a 70% improvement in multithreaded performance compared to the current EPYC "Turin" family. However, all of that is shaping up to come with a significant power cost, as AMD gears up to cool these chips through customized solutions.
14 Comments on AMD Prepares EPYC "Venice" Platform to Break the 1,000 W Power Barrier
I think it's going to be more of a what are we wasting everything on problem we have to tackle and not so much computers needing more power.
I'm writing this as i'm about to have nightcafe.studio generate a dumb image to keep my streak and credit generation going.
prompt: "a bold child confronting the evils"
I think the machines know i'm on to them!
Not to mention "super diamond" heatsinks...
A wattage number alone does not really say much.
Given how consistently AMD has delivered with RPYC, I find it much more likely to believe that they are claiming 70% more performance then a 5th gen core at the same core count.
1000W power draw for a server CPU isn't a barrier. There are barriers I suppose, 75W for a GPU in an x16 slot, 150W with a 6-pin connector, and so on. But 1000 is just a nice number. With 256 cores, 1400W is 5.5W per core.
500W with only 256 cores will likely mean the clocks will be very low. And by opening up the power envelope you can raise those clocks and provide the performance with it.
The desktop parts are perhaps twice as fast in single threaded compared to server(s) - and that is what i think is a big issue depending on your workload.
For some webhosting on a Ryzen is likely to be faster then on a Epyc - some software in the linux space is simply not optimized for multicore use and it just benefits better from faster single cores.
Look at the results for a previous CPU on that node; to give you a guesstimate of the outcome:
www.mediatek.com/press-room/mediatek-develops-chip-utilizing-tsmcs-2nm-process-achieving-milestones-in-performance-andpower-efficiency
Compared with the current-generation N3E process, N2P users can expect to see as much as an 18 percent increase in performance at the same power, an approximately 36 percent power reduction at the same speed, and a 1.2x increase in logic density.
www.tsmc.com/english/dedicatedFoundry/technology/platform_HPC_tech_advancedTechThe N2P technology provides a 5% performance uplift, while maintaining the same design rules as N2, and could account for the majority of N2 adoptions. N2P delivers an 18% speed improvement at the same power, a 36% power reduction at the same speed, 1.2 times logic density, and 1.15 times chip density over N3E.
There's different limits for everyone. Mine is the wall socket, or two wall sockets on different circuits.For a server it's probably the existing power supply versus swapping out HDDs for SSDs (to save some power, and boost the speed) against how big a CPU you can put in; in that scenario another one or two hundred watts can be OK. In some cases a power supply upgrade is possible, the amount of power going to the whole rack is the limit; in that case just move to a higher limit rack, for a lot more money.
I say the power and lower density ought to be 256 cores at several hundred watts, otherwise it's not going to accommodate my wall sockets, so I hope that's what's coming at 600W x 2CPUs with 256 cores each and a huge cache and many additional PCIe lanes at version 6.
So, not too far fetched.