Wednesday, December 13th 2017

AMD Confirms 2nd Generation Ryzen Processors to Debut in Q1-2018

At a press event, AMD confirmed that its 2nd generation Ryzen desktop processors will debut in Q1-2018 (before April). It also clarified that "2nd Generation" does not equal "Zen2" (a micro-architecture that succeeds "Zen"). 2nd Generation Ryzen processors are based on two silicons, the 12 nm "Pinnacle Ridge," which is a GPU-devoid silicon with up to eight CPU cores; and "Raven Ridge," which is an APU combining up to 4 CPU cores with an iGPU based on the "Vega" graphics architecture. The core CPU micro-architecture is still "Zen." The "Pinnacle Ridge" silicon takes advantage of the optical shrink to 12 nm to increase clock speeds, with minimal impact on power-draw.

AMD is also launching a new generation of chipset, under the AMD 400-series. There's not much known about these chipsets. Hopefully they feature PCIe gen 3.0 general purpose lanes. The second-generation Ryzen processors and APUs will carry the 2000-series model numbering, with clear differentiation between chips with iGPU and those without. Both product lines will work on socket AM4 motherboards, including existing ones based on AMD 300-series chipset (requiring a BIOS update). AMD is reserving "Zen2," the IPC-increasing successor of "Zen" for 2019. The "Mattise" silicon will drive the multi-core CPU product-line, while the "Picasso" silicon will drive the APU line. Both these chips will run on existing AM4 motherboards, as AMD plans to keep AM4 as its mainstream-desktop socket till 2020.
Source: WCCFTech
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101 Comments on AMD Confirms 2nd Generation Ryzen Processors to Debut in Q1-2018

#1
bug
Rauelius said:
- Athlon 2240x - 3.2Ghz/3.5Ghz Boost, 2-Cores / 4 Threads - Price: $69 - Oct.

- Ryzen 2410x - 3.3Ghz/3.7Ghz Boost, 4-Cores No SMT - Price: $99 - Sept.
- Ryzen 2430x - 3.6Ghz/4.0Ghz Boost, 4-Cores No SMT - Price $129 - Late August

- Ryzen 2550x - 3.5Ghz/3.9Ghz Boost, 4-Cores / 8-Threads - Price $169 - May
- Ryzen 2570x - 3.8Ghz/4.2Ghz Boost, 4-Cores / 8-Threads - Price $199 - April

- Ryzen 2650x - 3.7Ghz/4.1Ghz Boost, 6-Cores/ 12-Threads - Price $239 - June
- Ryzen 2670x - 4.2Ghz/4.5Ghz Boost, 6-Cores/ 12-Threads - Price $279 - April

- Ryzen 2730x - 3.6Ghz/4.0Ghz Boost, 8-Cores/ 16-Threads - Price $329 - March
- Ryzen 2750x - 3.9Ghz/4.2Ghz Boost, 8-Cores/ 16-Threads - Price $409 - March
- Ryzen 2770x - 4.2Ghz/4.5Ghz Boost, 8-Cores/ 16-Threads - Price $549 - Late Feb.

- Ryzen TR 2930x - 4.0Ghz/4.5Ghz Boost, 10-Cores/ 20 Threads - Price $699 - July
- Ryzen TR 2950x - 3.8Ghz/4.2Ghz Boost, 12-Cores/ 24-Threads - Price $849 - July
- Ryzen TR 2970x - 3.7Ghz/4.1Ghz Boost, 16-Cores/ 32-Threads - Price $999 - June

- Ryzen TR 2990x - 3.6Ghz/4.0Ghz Boost, 24 Cores/ 48 Threads - Price $1499 - Oct.
Nice list. Do you have a source for it or is it just your letter to Santa?
Posted on Reply
#2
sergionography
bug said:
If there were architectural changes, AMD would be touting them all over the place. The term "optical shrink" used in the article means no architectural changes. But you;re free to bet on whatever you want, of course.
There wont be major architectural changes on a high level to be touted as a new architecture, but being that its a new revision on a refined node it is likely to sustain higher clocks for better single threaded performance. So while IPC might be the same theoretically, real world results might still show what appears to be better IPC due to better power management etc. Keep in mind that cpus these days have become very dynamic with their clocks so measuring IPC isnt exactly as accurate as it used to be. And although ryzen was successful, AMD mentioned multiple times about it being a "worst case scenario", which i think is pretty obvious seeing how efficient it is yet still hits a block around 4.1ghz without even coming close to max thermal limits.
Posted on Reply
#4
bug
sergionography said:
There wont be major architectural changes on a high level to be touted as a new architecture, but being that its a new revision on a refined node it is likely to sustain higher clocks for better single threaded performance. So while IPC might be the same theoretically, real world results might still show what appears to be better IPC due to better power management etc. Keep in mind that cpus these days have become very dynamic with their clocks so measuring IPC isnt exactly as accurate as it used to be. And although ryzen was successful, AMD mentioned multiple times about it being a "worst case scenario", which i think is pretty obvious seeing how efficient it is yet still hits a block around 4.1ghz without even coming close to max thermal limits.
If we look back at what intel did, even when they actually claimed architectural improvements, we were only getting something like 3-5% better IPC and even then, it was situational. As such, I don't expect "a new revision on a refined node" to yield anything measurable.

But like I said above, an unchanged design running a few hundred MHz faster is already enough to put pressure on Intel.
Posted on Reply
#5
jahramika
bug said:
If there were architectural changes, AMD would be touting them all over the place. The term "optical shrink" used in the article means no architectural changes. But you;re free to bet on whatever you want, of course.
This is not a Ryzen launch where they needed the attention to get a new product out to people. Ryzen is already here and known about they will dont and will no talk about things until the actually release them.
Posted on Reply
#6
Kaotik
Mirkoskji said:
Nvidia volta will be manufactured in12nm. Current Titan V is 12nm
If GloFo and Samsung didn't have 14nm nodes it would be called 16nm (It was renamed to 12nm shortly before launch due market situation, similar to how GloFos upcoming "12nm" was supposed to be called 14nm but because TSMC called their 16nm refresh 12nm, GloFo calls their 14nm refresh 12nm too)
Posted on Reply
#7
ShurikN
Kaotik said:
If GloFo and Samsung didn't have 14nm nodes it would be called 16nm (It was renamed to 12nm shortly before launch due market situation, similar to how GloFos upcoming "12nm" was supposed to be called 14nm but because TSMC called their 16nm refresh 12nm, GloFo calls their 14nm refresh 12nm too)
Posted on Reply
#8
dicktracy
It’ll be more of the same. Don’t put too much hype into it.
Posted on Reply
#9
looncraz
theoneandonlymrk said:
Which is why I implied it was 14nm+++ they reduced only one gate dimension to 12nm at best and greatly improved some other geometries to gain an alleged 30-40% die area improvement but its not a true new node like 10nm is and 7nm will be as you know:)

Err as far as i remember the 14nm+++ got talked about then forgotten about as it got renamed 12nm ,or that's how i percieved it but who knows what dimensions it's really packing these days.
12nm is 15% smaller than 14nm. That's even Global Foundries' claims regarding 12LP.

It should also result in a 10~15% improvement in gained efficiency due to 15% area shrinkage, but then it looks like they used that to boost performance (transistor switching rate / current) by 10~15%.

This is a proper step from 14nm to 12nm. 15% smaller than 14... is 12.17, you would NEVER expect 30% from this.

notb said:
As I've mentioned many times: Intel had a similar performance improvement in the same period. So it's really nothing special.
No they didn't. Sandy Bridge bested Bulldozer out of the gate. Intel only gained about 25% total IPC over several generations. They did better with STOCK frequencies, but not much beter with overclocking (my i7-2600k could do 5GHz... and only hit ~72C). AMD went from 50% behind to a near dead heat in ONE generation.

bug said:
If there were architectural changes, AMD would be touting them all over the place. The term "optical shrink" used in the article means no architectural changes. But you;re free to bet on whatever you want, of course.
The terminology used in the article isn't from AMD. AMD has remained silent regarding Pinnacle Ridge. It's a refresh on a new process.

The "Zen" part of the design is only a small component. The caches, CCX, IP blocks, IMC, infinity fabric, and everything else are NOT Zen - they're Zepplin. Pinnacle Ridge is a new Zepplin iteration - meaning any, or all, of those things could be revised... and it'd still be a Zen-powered architecture.

But, to be clear, it's likely the core has seen some minor revisions as part of its shrink.
Posted on Reply
#11
EarthDog
looncraz said:
No they didn't. Sandy Bridge bested Bulldozer out of the gate. Intel only gained about 25% total IPC over several generations. They did better with STOCK frequencies, but not much beter with overclocking (my i7-2600k could do 5GHz... and only hit ~72C). AMD went from 50% behind to a near dead heat in ONE generation.
But the person you quoted said 'period'. So SB/Bulldozer to now. Sure, Intel was more iterative it wasn't a 50% jump. AMD just got off their arse with Zen, finally. :)

I don't expect to see any IPC improvements... but hopeful for a couple % anyway.
Posted on Reply
#12
R0H1T
EarthDog said:
But the person you quoted said 'period'. So SB/Bulldozer to now. Sure, Intel was more iterative it wasn't a 50% jump. AMD just got off their arse with Zen, finally. :)

I don't expect to see any IPC improvements... but hopeful for a couple % anyway.
Does fixing XFR count, the one in mobile RR is what it was originally supposed to be!
Posted on Reply
#13
theoneandonlymrk
looncraz said:
12nm is 15% smaller than 14nm. That's even Global Foundries' claims regarding 12LP.

It should also result in a 10~15% improvement in gained efficiency due to 15% area shrinkage, but then it looks like they used that to boost performance (transistor switching rate / current) by 10~15%.

This is a proper step from 14nm to 12nm. 15% smaller than 14... is 12.17, you would NEVER expect 30% from this.



No they didn't. Sandy Bridge bested Bulldozer out of the gate. Intel only gained about 25% total IPC over several generations. They did better with STOCK frequencies, but not much beter with overclocking (my i7-2600k could do 5GHz... and only hit ~72C). AMD went from 50% behind to a near dead heat in ONE generation.



The terminology used in the article isn't from AMD. AMD has remained silent regarding Pinnacle Ridge. It's a refresh on a new process.

The "Zen" part of the design is only a small component. The caches, CCX, IP blocks, IMC, infinity fabric, and everything else are NOT Zen - they're Zepplin. Pinnacle Ridge is a new Zepplin iteration - meaning any, or all, of those things could be revised... and it'd still be a Zen-powered architecture.

But, to be clear, it's likely the core has seen some minor revisions as part of its shrink.
Unless their were defects a die shrink usually contains few changes to layout and those that are usually lie in the tweaking geometries via masking line ,so tweaked masks and process equals new node , it does to fabs nowadays I agree but it's not all that, but it is what AMD need now and might be my next pc so here's to hoping.
Posted on Reply
#14
looncraz
theoneandonlymrk said:
Unless their were defects a die shrink usually contains few changes to layout and those that are usually lie in the tweaking geometries via masking line ,so tweaked masks and process equals new node , it does to fabs nowadays I agree but it's not all that, but it is what AMD need now and might be my next pc so here's to hoping.
A direct shrink would be surprising, though not necessarily a problem. AMD needs to increase frequency more than anything and they undoubtedly have some critical path issues (even at ~2V and LN2 we're only seeing a little over 5GHz). Addressing those would be a very good idea... if they know where the issues are (I suspect it's in one of the 8 or so cache types used - 5 types for the L1 alone). The CPU can detect data errors when instability strikes and locks the data buses to prevent propagation - that is what freezes the whole system (this behavior seems to have changed with AGESA 1070+ ... or more error correction is attempted).

Given that the most likely frequency bottleneck is in the caches - and process changes have an outsized impact on those same caches (since they're just arrays of memory cells that are usually the focus on process development due to their physical simplicity and uniformity) - AMD might anticipate that they can achieve their goals without any core updates.

Memory latency is certainly a problem - and the infinity fabric could certainly use some more optimization... the SATA and PCI-e controllers could also use some fine-tuning. All of this is outside of the core and could lead to higher IPC (there's safely still a good 10% more IPC left unused in that core!) - maybe enough to match/beat stock 8-core Skylake-X in single threaded performance... while having lower average inter-core latency, higher average SMT performance, and slightly more efficiency.

Now that I have my 1700X at 4GHz and 3200 CL14, I need 15% from this point to consider upgrading. A safe 4.6GHz 8-core overclock would entice me to upgrade - my current CPU would find its way into a production machine, and then I'd have its 1700 to sale or repurpose. 10% could entice me if I can do it with < $100 investment.
Posted on Reply
#15
yogurt_21
so 2019 is Zen 2 then. my 4790K should be just fine until then. VGA will come sooner but the rest should be fine. Then I can see if its a return to AMD after what will be 12 years on Intel for the main rig or just another Intel refresh...tbh just for something different it'd be nice to go back. Last main rig AMD CPU was the FX-62. Granted there have only been 3 intel in that time (Q6700>i7-950>i7-4790K)

Hoping AMD keeps rolling and Zen 2 kicks butt.
Posted on Reply
#16
efikkan
looncraz said:
A direct shrink would be surprising, though not necessarily a problem.
"12nm" is just a refined process, not a die shrink anyway.

looncraz said:

AMD needs to increase frequency more than anything and they undoubtedly have some critical path issues

Given that the most likely frequency bottleneck is in the caches - and process changes have an outsized impact on those same caches
Sure, the frequency bottlenecks are due to cirical paths. A new stepping might tweak a few things, but there will be no major overhauls until "Zen2". We know there are timing issues with the micro-op cache, among other things.

looncraz said:

Memory latency is certainly a problem - and the infinity fabric could certainly use some more optimization... the SATA and PCI-e controllers could also use some fine-tuning. All of this is outside of the core and could lead to higher IPC (there's safely still a good 10% more IPC left unused in that core!) - maybe enough to match/beat stock 8-core Skylake-X in single threaded performance... while having lower average inter-core latency, higher average SMT performance, and slightly more efficiency.
The primary component of memory latency is DRAM latency, which is a constant. The memory controller could use some tweaks, but this is not the bottleneck of Zen.
The rest of what you mention doesn't impact IPC.

Zen has more computational resources than Skylake, so if it can keep its ALUs and FPUs fed, it outperforms Skylake. This is why certain applications scale well when the prefetcher isn't bottlenecking the CPU. Designing a better front-end will close the gap vs. Intel.
Posted on Reply
#17
looncraz
efikkan said:
"12nm" is just a refined process, not a die shrink anyway.
Semantics

12LP is a refined 14nm LPP, which is a refined 16nm, which is a refined 20nm, which is a refined... you get the idea. Not every refinement makes it to full production - some do. Not every die shrink has to be of the same magnitude. Technically, EVERY process that has a smaller feature size is a die shrink - and 12LP has 15% smaller features than 14LPP. Process refinements don't typically have smaller feature sizes, just tweaks to chemistry, processes, libraries, and (sometimes) material.

efikkan said:

Sure, the frequency bottlenecks are due to cirical paths. A new stepping might tweak a few things, but there will be no major overhauls until "Zen2". We know there are timing issues with the micro-op cache, among other things.
Precisely why I think AMD would take the time to address at least some of these issues. Little tweaks that take only days to implement while they are already revisiting a component or pathway for the shrink can go a long way. They may, by now, have a few revisions to prevent a repeat of the segfault issue - in the very least.

efikkan said:


The primary component of memory latency is DRAM latency, which is a constant. The memory controller could use some tweaks, but this is not the bottleneck of Zen.
The rest of what you mention doesn't impact IPC.
Not on Ryzen. The same tests where Intel achieves 19ns Ryzen may achieve only 90~100ns. 20~40ns of that is just the infinity fabric latency. The rest may be the message bundling I assume is happening - probably a highly variable latency. Otherwise RAM traffic would flood the infinity fabric. AMD may be able to take away some of the variability and shave 20ns or so. The main benefit of faster memory on Ryzen is that it reduces latency - this can be seen in applications which are not usually sensitive to memory performance actually responding (such as Cinebench).

Ryzen can't keep the cores fed when volatile data is in play (which is common in multi-thread synchronization), so every little bit here will result in higher IPC, albeit not in all scenarios - but IPC, for CPUs, is an average in any event.

efikkan said:

Zen has more computational resources than Skylake, so if it can keep its ALUs and FPUs fed, it outperforms Skylake. This is why certain applications scale well when the prefetcher isn't bottlenecking the CPU. Designing a better front-end will close the gap vs. Intel.
Zen's front end is capable of extracting near complete ILP. Still, there are a few scenarios where being only a six issue design has drawbacks compared to Intel's peak seven issue design. I really don't know what would be the path of least resistance to address that... that would take some time to consider (and lots of tedious math... dang it, now I'm tempted...).
Posted on Reply
#18
Gmr_Chick
Rauelius said:
- Athlon 2240x - 3.2Ghz/3.5Ghz Boost, 2-Cores / 4 Threads - Price: $69 - Oct.

- Ryzen 2410x - 3.3Ghz/3.7Ghz Boost, 4-Cores No SMT - Price: $99 - Sept.
- Ryzen 2430x - 3.6Ghz/4.0Ghz Boost, 4-Cores No SMT - Price $129 - Late August

- Ryzen 2550x - 3.5Ghz/3.9Ghz Boost, 4-Cores / 8-Threads - Price $169 - May
- Ryzen 2570x - 3.8Ghz/4.2Ghz Boost, 4-Cores / 8-Threads - Price $199 - April

- Ryzen 2650x - 3.7Ghz/4.1Ghz Boost, 6-Cores/ 12-Threads - Price $239 - June
- Ryzen 2670x - 4.2Ghz/4.5Ghz Boost, 6-Cores/ 12-Threads - Price $279 - April

- Ryzen 2730x - 3.6Ghz/4.0Ghz Boost, 8-Cores/ 16-Threads - Price $329 - March
- Ryzen 2750x - 3.9Ghz/4.2Ghz Boost, 8-Cores/ 16-Threads - Price $409 - March
- Ryzen 2770x - 4.2Ghz/4.5Ghz Boost, 8-Cores/ 16-Threads - Price $549 - Late Feb.

- Ryzen TR 2930x - 4.0Ghz/4.5Ghz Boost, 10-Cores/ 20 Threads - Price $699 - July
- Ryzen TR 2950x - 3.8Ghz/4.2Ghz Boost, 12-Cores/ 24-Threads - Price $849 - July
- Ryzen TR 2970x - 3.7Ghz/4.1Ghz Boost, 16-Cores/ 32-Threads - Price $999 - June

- Ryzen TR 2990x - 3.6Ghz/4.0Ghz Boost, 24 Cores/ 48 Threads - Price $1499 - Oct.
bug said:
Nice list. Do you have a source for it or is it just your letter to Santa?
I was going to say the same thing, Bug. I'd like to know where he gets his crystal ball from :kookoo:
Posted on Reply
#19
notb
looncraz said:

No they didn't. Sandy Bridge bested Bulldozer out of the gate. Intel only gained about 25% total IPC over several generations. They did better with STOCK frequencies, but not much beter with overclocking (my i7-2600k could do 5GHz... and only hit ~72C). AMD went from 50% behind to a near dead heat in ONE generation.
Oh please, leave those IPC bollocks for someone else. ;-)
Sandy Bridge to Kaby Lake is ~+30% performance in similar price ranges (like: i5 2500 -> 7500). And if one is also concerned by power consumption, these went down considerably as well.
(And that's still comparing to Kaby, while I SHOULD compare to Coffee Lake, since it's the direct competitor for Ryzen: 50%, easily.)

And yes, Bulldozer was a very poor architecture - way behind Sandy for sure, so the potential for improvement at Blues was smaller.
If you compare performance since when AMD and Intel had similar products, you'll see it's pretty much the same in long period. In the end it's just some transistors and silicon. There's no reason why the performance should differ significantly, ever. The features and stability, however, can differ. And they do.

So once again: why do you stress so much that AMD did it in "ONE generation"? Intel might have also stopped releasing products between Sandy Bridge and Coffee Lake and make a >50% "in one generation". Thankfully they didn't.
You might be trying to complement AMD for a large achievement, but what you're actually saying is: they were totally ignoring their customers for 5 years.
Posted on Reply
#20
Konceptz
If we can get 4.0-4.2ghz stable or higher while waiting for Ryzen 2 i'll be happy. I still on my FX-8350 waiting for Ryzen +
Posted on Reply
#21
efikkan
looncraz said:
Semantics
12LP is a refined 14nm LPP, which is a refined 16nm, which is a refined 20nm, which is a refined... you get the idea. Not every refinement makes it to full production - some do. Not every die shrink has to be of the same magnitude. Technically, EVERY process that has a smaller feature size is a die shrink - and 12LP has 15% smaller features than 14LPP. Process refinements don't typically have smaller feature sizes, just tweaks to chemistry, processes, libraries, and (sometimes) material.
The node is the same, the effective density may be marginally changed. Like GV100 is ~3% denser than GP100.
Intel call their refinements of their 14nm process 14FF+ and 14FF++, TSMC and Samsung call theirs by new numbers.

looncraz said:

Not on Ryzen. The same tests where Intel achieves 19ns Ryzen may achieve only 90~100ns. 20~40ns of that is just the infinity fabric latency.

Ryzen can't keep the cores fed when volatile data is in play (which is common in multi-thread synchronization), so every little bit here will result in higher IPC, albeit not in all scenarios - but IPC, for CPUs, is an average in any event.
The memory latency is only impacted by infinity fabric when crossing the infinity fabric first.
Core interconnection doesn't impact IPC.
Posted on Reply
#22
looncraz
notb said:
Oh please, leave those IPC bollocks for someone else. ;-)
Sandy Bridge to Kaby Lake is ~+30% performance in similar price ranges (like: i5 2500 -> 7500). And if one is also concerned by power consumption, these went down considerably as well.
(And that's still comparing to Kaby, while I SHOULD compare to Coffee Lake, since it's the direct competitor for Ryzen: 50%, easily.)

And yes, Bulldozer was a very poor architecture - way behind Sandy for sure, so the potential for improvement at Blues was smaller.
If you compare performance since when AMD and Intel had similar products, you'll see it's pretty much the same in long period. In the end it's just some transistors and silicon. There's no reason why the performance should differ significantly, ever. The features and stability, however, can differ. And they do.

So once again: why do you stress so much that AMD did it in "ONE generation"? Intel might have also stopped releasing products between Sandy Bridge and Coffee Lake and make a >50% "in one generation". Thankfully they didn't.
You might be trying to complement AMD for a large achievement, but what you're actually saying is: they were totally ignoring their customers for 5 years.
Let's go from Sandy Bridge all of the way to Skylake. At 3GHz, fixed, which is where I do all of my IPC testing (as does Anandtech).




Intel absolutely made very few strides in performance. Coffee Lake IPC largely remains unchanged from Skylake.

It takes four or five years to design a new CPU architecture. AMD has been working on Zen since the inception of Piledriver.

Intel made a misstep with the Pentium 4 - AMD made a misstep with Bulldozer. Neither company was able to rectify the situation quickly.
Posted on Reply
#23
fizhsmile
Just wondering here, why mobile cpus are growing up so fast I mean Qualcomm and Samsung able to improve the performance in their mobile cpus Snapdragon & Exynoss up to 20-30% or even double the performance from previous generation. But why in desktop, we only able to get like 5% performance increase from previous generation? (IYKWIM). Well I dont know about architechture, process of shrinking, etc. Is this because the lack of competition or it is really hard to get big performance increase?. Can somebody kindly explain this to me? :D
Posted on Reply
#24
EarthDog
looncraz said:
Let's go from Sandy Bridge all of the way to Skylake. At 3GHz, fixed, which is where I do all of my IPC testing (as


Intel absolutely made very few strides in performance. Coffee Lake IPC largely remains unchanged from Skylake..
looks like close to 25% average there, no? That also doesnt include the 5% from SB to IB.
Posted on Reply
#25
looncraz
efikkan said:
The node is the same, the effective density may be marginally changed. Like GV100 is ~3% denser than GP100.
Intel call their refinements of their 14nm process 14FF+ and 14FF++, TSMC and Samsung call theirs by new numbers.
Let's be honest here: neither of us knows what Global Foundries did to achieve a 15% reduction in area. 14nm LPP is rather mature and dense as it is, so feature size changes would likely be the chosen route... by employing existing GF technology.

efikkan said:

The memory latency is only impacted by infinity fabric when crossing the infinity fabric first.
Core interconnection doesn't impact IPC.
The IMC is a client of the IF. This means it needs to operate with discrete packet transactions. It's an absolute requirement that data is fed into a buffer before sending data (either to the memory sticks or to the requesting client) - otherwise you stand a good chance of flooding the IF with packets. It's a trade-off between bandwidth and latency. I've had to implement these things (in software) before - it's pretty simple... and VERY effective. But always with the downside of higher latency.

EarthDog said:
looks like close to 25% average there, no? That also doesnt include the 5% from SB to IB.
24%... if you include the outlier 69% boost. 19% without it.

And, yes, it includes ALL jumps.

POV-Ray is *almost* an outlier. IPC improvement is only 16.7% without it... from Sandy Bridge to Skylake. So the "fair" IPC improvement range is 16~20%.... with FOUR generations of products (well, five or six now, depending on how you count).
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