Tuesday, December 23rd 2025

AMD "Zen 6" SKUs with 3D V-Cache Could Pack Up to 288 MB of Cache

Dec 23rd, 2025 11:48 Discuss (77 Comments)

AMD's upcoming "Zen 6" client processors are expected to continue the trend of offering optional SKUs with 3D V-Cache, similar to their predecessors. However, these new processors might feature significantly larger cache capacities compared to the current "Zen 5" SKUs in the "Granite Ridge" family. According to HXL on X, the single-CCD version will include 144 MB of 3D V-Cache, while the dual-CCD configuration will have 288 MB of cache. This suggests that AMD will maintain its familiar CPU design with a client I/O die and two separate CCDs, each benefiting from increased cache capacity.

This approach is quite similar to Intel's upcoming "Nova Lake" processors, which are also set to receive a substantial boost in cache capacity through the big Last Level Cache (bLLC). Rumors suggest that these will offer 144 MB for SKUs with a single compute die and 288 MB for those with two compute dies. Intel already employs bLLC in its "Clearwater Forest" server processors as a passive interposer, integrating local cache beneath active tiles. Including this technology in standard gaming chips could significantly enhance performance, positioning them as strong competitors against the upcoming "Zen 6" processor family.

For "Zen 6," AMD plans to place the CPU CCD on TSMC's N2P 2 nm node variant and build the cIOD on the N3P 3 nm node. Additionally, the increased cache capacity will be complemented by advanced x86-64 instruction extensions like AVX512_BMM, AVX512_FP16, AVX_NE_CONVERT, AVX_IFMA, and AVX_VNNI_INT8, among others. This is particularly noteworthy because 16-bit AVX-512 calculations will now be possible on consumer-oriented desktop CPUs, providing an extra performance boost with a fast memory pool nearby.

Source: HXL on X

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77 Comments on AMD "Zen 6" SKUs with 3D V-Cache Could Pack Up to 288 MB of Cache

#26

ymdhis

evernessinceHigh idle consumption on AMD is in large part due to the dual chipset solution that every reviewer tests with, IO die actual makes up the smaller portion of that. You can see this when comparing the Ryzen 5000 series vs the Ryzen 7000 series, where the 5000 series has identical power consumption to Intel parts:

www.techpowerup.com/review/intel-core-ultra-7-265k/24.html

Although you'd really like to see lower idle numbers than 50w on desktop in general. It can be hard though when the chipset takes 7-9w by itself.

It is said that Zen 6 will use new interconnects for the IO die, the same ones as one Strix Halo, which will reduce the idle power usage by as much as ~10W. Currently the chiplet Ryzens have the SoC (the IO die) use as much as 15W, while the monolithic Ryzen APUs and Strix Halo reach as low as 3-4W.

Other than that the thing most responsible for high idle power is motherboards overspeccing on the VRMs.

#27

windwhirl

CornyOCOh yeah boy, 12 core 288MB cache X3D CPU around 6GHz speed per core. I am more hyped for Zen 6 than any other hardware rn.

From the post, it seems like 288 MB is only for dual CCD SKUs. The single CCD SKUs will get half that.

#28

Unregistered

I'm wondering if this is a response to AMD possibly feeling threatened by Nova Lake. 🤔

#29

windwhirl

docnorthBtw a single CCD 12 core CPU is rumoured, could it feature 216 MB of 3D V-Cache?

Why would it? The V-cache so far seems to be made in a single size for all. And from this announcement, it seems it will be just one piece of V-cache for single CCDs, two pieces for dual CCDs. Doesn't matter what the actual core configuration is, only whether there is one or two CCDs.

#30

Makaveli

oobymachIntel finally had enough of AMD running the cache game, they're probably going to take back the lead.

That remains yet to be seen.

This will be a first gen intel cache solution vs Gen 3 by the time the Zen 6 version is out.

And with them having equal sizes the next battle will be who has the lowest latency cache.

windwhirlFrom the post, it seems like 288 MB is only for dual CCD SKUs. The single CCD SKUs will get half that.

agree the 12 core single CCD part should have 144mb of cache.

#31

Eliad Buchnik

MakaveliTrue and interesting that both Intel and AMD will be equal in size for this.

Another question will be who will have the lower latency cache plus we should be getting higher 1:1 speeds with DDR5 8000 and faster IF speeds on Zen 6 so alot of questions on what performance will look like with the new I/O die. This also means we should finally see a reduction on power consumption at idle on AMD.

I'm looking forward to replacing my 9800X3D with the 12 core single CCD X3D variant when its released.

Zen 6 should be using tsmc integered fan-out on substrate just like Strix halo, meaning they are basically moving from serial connection and all the associated SerDes to wide parallel connection, both latency fabric speed should improve drastically between IOD and CCD.

#32

john_

First it was the number of cores, now it is the cache. I wonder the prices. Are we going to see the come back of the $999 mainstream CPU?

By the way (AI reply)

The top-end Xeon for 2016 was largely the Intel Xeon E5-2600 v4 (Broadwell-EP) family, with the flagship being the E5-2699 v4, offering 22 cores/44 threads, 55MB L3 Cache, a 2.2GHz base (3.6GHz Turbo), and 145W TDP

#33

TheinsanegamerN

And with only 2 mortgages, you can afford the RAM to go with it!

Grimlingthe question is, how much more performance will we get with that amount of cache in gaming?

My guess is substantial, in games that love cache. As they get more memory hungry the 64mb 3d cache in the current models will run out.

igormpI personally doubt there'll be any, but we shall see once such products become available and benchmarks take place.

People said the same about the 5800x3d before it came out. Then they said it again with the 7800x3d, that the faster memory would make the cache obsolete.

Now we're gonna go 3 for 3.

#34

kondamin

TheinsanegamerNMy guess is substantial, in games that love cache. As they get more memory hungry the 64mb 3d cache in the current models will run out.

well yes that’s the point of l3, it’s a place where excess is stored so ram or worse latency wise doesn’t need to be accessed.
More is better but there is just a select number of process task that benefit from large caches

#35

SRB151

oobymachIntel finally had enough of AMD running the cache game, they're probably going to take back the lead.

This assumes Nova Lake arch will beat Zen 6. Intel hasn't beaten Zen 5 yet. Keep in mind, Intel's answer for everything is just add more cores. Games really don't scale much past 8 cores so far. Intel has a lot of work before they can declare themselves at parity.

#36

LiKenun

SRB151Keep in mind, Intel's answer for everything is just add more cores.

TBF, they have APX this time and are bringing back 512-bit vector units? I wouldn’t rest on my laurels knowing what Intel has in store for Nova Lake.

#37

Punkenjoy

So it would probably be a 96 MB chip on top or under the CCD containing 48 MB L3 cache. I wonder what would be the performance gains in gaming or if we would go into diminishing return territory.

#38

shuffy_losys

TheinsanegamerNMy guess is substantial, in games that love cache. As they get more memory hungry the 64mb 3d cache in the current models will run out.

It's not a general assumption one can make. It depends entirely on what's going on in game. For example, Chips and Cheese did some analysis on the 7950X3D

Game	X3D Zen 4 L3 Hit Rate	X3D Zen 4 Instructions Retired/Active Thread	Normal Zen 4 L3 Hit Rate	Normal Zen 4 Instructions Retired/Active Thread
Gunner, HEAT, PC! (GHPC)	78%	1.27	58.65%	1.15
Cyberpunk 2077	63.74%	1.43	45.99%	1.26
DCS	92.42%	1.73	89.06%	1.77
Call of Duty: Black Ops Cold War Zombies	68.68%	0.85	46.51%	0.7

The "Instructions retired/active thread" metric is similar to IPC; the higher the number, the more instructions were run to completion. They focused a little more on CoD because of its low IPC and found the biggest bottleneck was still the front end (which is basically instruction fetching, decoding, and branch prediction/speculation), which L3 cache doesn't necessarily help here.

In any case, considering that tripling the amount of L3 cache only really brought about maybe 15% on-average instruction throughput improvement, then I'd imagine tripling it again would do the same at best, if anything at all. Which honestly, I don't find sustainable in the long run.

#39

SRB151

LiKenunTBF, they have APX this time and are bringing back 512-bit vector units? I wouldn’t rest on my laurels knowing what Intel has in store for Nova Lake.

I wouldn't hang my hat on that. I was referring to gaming, since x3d is a mixed bag on productivity uses. And they had better have improved the 512 wide system. the reason they ditched it was full 512 killed clock speeds and ran hot at the same time. It also takes time for new instructions to be picked up by programmers. AMD has upgraded theirs as well on Zen 6.

For the record, I think there was a line of Epyc x3d cpus, and again, they were for specific use cases, and didn't do much for many tasks.

#40

Tek-Check

SRB151I was referring to gaming, since x3d is a mixed bag on productivity uses.

Productivity performance on X3D CPUs has substantially improved with Zen5. The top X3D SKU is actually faster than vanilla 9950X in almost all productivity workloads.
www.techpowerup.com/review/amd-ryzen-9-9950x3d/28.html

#41

docnorth

windwhirlWhy would it? The V-cache so far seems to be made in a single size for all. And from this announcement, it seems it will be just one piece of V-cache for single CCDs, two pieces for dual CCDs. Doesn't matter what the actual core configuration is, only whether there is one or two CCDs.

Until now it's one size for all 8-core CCDs regardless of enabled cores. A 12-core CCD might (or might not, due to smaller node) be larger, that's why I'm asking.

#42

Fishymachine

I wanted to say that number doesn't make sense, but I remembered Zen 6 is moving to 12 core CCD, so 48 + 144 = 192 MB L3, which is exactly 50% above current 8 core offerings. So in conclusion, I might plonk a 10800X3D in lieu of my current 7600X

#43

Nathaaab

SRB151Keep in mind, Intel's answer for everything is just add more cores.

Yes, because keep in mind not everyone is only playing games on their computers.

SRB151Intel hasn't beaten Zen 5 yet.

TPU launch review for Arrow Lake CPUs shows it's within 1% of Zen 5 competitors at 720p on a test system using slow 6000MT/s RAM. The only thing they haven't beaten is Zen5 3D

#44

JMccovery

FishymachineI wanted to say that number doesn't make sense, but I remembered Zen 6 is moving to 12 core CCD, so 48 + 144 = 192 MB L3, which is exactly 50% above current 8 core offerings. So in conclusion, I might plonk a 10800X3D in lieu of my current 7600X

I think it'll be 144MB total: 48MB in the CCD + 96MB Vcache.

#45

lemans24

SRB151This assumes Nova Lake arch will beat Zen 6. Intel hasn't beaten Zen 5 yet. Keep in mind, Intel's answer for everything is just add more cores. Games really don't scale much past 8 cores so far. Intel has a lot of work before they can declare themselves at parity.

The fact that Intel MAY release Nova Lake with 144mb cache per compute tile and for both tiles too...does not that at least give a hint that Intel is maybe concentrating on clawing back the over 30% performance in gaming that x3d cache give Amd Ryzen over Arrow Lake?? Sounds like Intels answer to Amd is a massive amout of L3 cache. Why are you complaining since it has definitely worked for Amd for 3 generations now and Intel is following in that same path!!. We are now going to hopefully get some amazing competition to most likely bring down prices for both cpu types. Is that not better than continuing to just dump on Inte?? I really don't care who is fastr in gaming performance between Amd and Intel just that they bring out the best version possible and the public decides for themselves.

#46

LiKenun

SRB151It also takes time for new instructions to be picked up by programmers.

APX is free though—in terms of developer effort for anyone not writing the compiler itself. For compiled software, it’s a recompilation with a compiler that can emit APX instructions. For virtual runtimes (e.g., the Java Virtual Machine), it’s upgrading the JIT compiler, with no rebuilding of the application itself needed.

I’m surprised that the .NET 10 runtime already supports AVX10.2 given how long the team dragged out implementing AVX-512 intrinsics support.

#47

shuffy_losys

LiKenunFor compiled software, it’s a recompilation with a compiler that can emit APX instructions.

For development teams, the compiler (and really toolchains in general) rarely get updated, especially for larger projects. Unless there's an actual deficiency somewhere, which usually means a feature requirement that the current system doesn't support, otherwise it's a case of "don't fix what isn't broke"

The goal should always be make correct software first. You can add performance later.

#48

Doctor Who

shuffy_losysFor development teams, the compiler (and really toolchains in general) rarely get updated, especially for larger projects. Unless there's an actual deficiency somewhere, which usually means a feature requirement that the current system doesn't support, otherwise it's a case of "don't fix what isn't broke"

The goal should always be make correct software first. You can add performance later.

The goal should always be make correct software first. You can add performance later?
Couldn't Agree More!

#49

Wirko

AleksandarKIntel already employs bLLC in its "Clearwater Forest" server processors as a passive interposer, integrating local cache beneath active tiles

A small correction - this is not a passive interposer because it contains transistors, which are active electronic devices.

#50

LiKenun

shuffy_losysFor development teams, the compiler (and really toolchains in general) rarely get updated, especially for larger projects. Unless there's an actual deficiency somewhere, which usually means a feature requirement that the current system doesn't support, otherwise it's a case of "don't fix what isn't broke"

It’s probably industry-dependent. My development experience has largely been on the side of updating large projects. “Broke” can be as simple as “this runtime is out-of-support and Microsoft won’t help if you continue to use it” or “these libraries are out of compliance because they have known security vulnerabilities now” kind of things. In time, everything becomes “broke” and will require work to bring it up to date.

In my case, my stacks don’t give me the choice to use or avoid new CPU features. Either Oracle/Microsoft blesses the new LTS JVM/.NET runtimes with support and the existing application code gains the performance boost, or not. There is no choice in this matter for me.

shuffy_losysThe goal should always be make correct software first. You can add performance later.

Is this your way of saying that the software will never be correct and the time to add performance will always be in the distant horizon. 😛

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AMD "Zen 6" SKUs with 3D V-Cache Could Pack Up to 288 MB of Cache

77 Comments on AMD "Zen 6" SKUs with 3D V-Cache Could Pack Up to 288 MB of Cache

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