Tuesday, December 23rd 2025
AMD "Zen 6" SKUs with 3D V-Cache Could Pack Up to 288 MB of Cache
AMD's upcoming "Zen 6" client processors are expected to continue the trend of offering optional SKUs with 3D V-Cache, similar to their predecessors. However, these new processors might feature significantly larger cache capacities compared to the current "Zen 5" SKUs in the "Granite Ridge" family. According to HXL on X, the single-CCD version will include 144 MB of 3D V-Cache, while the dual-CCD configuration will have 288 MB of cache. This suggests that AMD will maintain its familiar CPU design with a client I/O die and two separate CCDs, each benefiting from increased cache capacity.
This approach is quite similar to Intel's upcoming "Nova Lake" processors, which are also set to receive a substantial boost in cache capacity through the big Last Level Cache (bLLC). Rumors suggest that these will offer 144 MB for SKUs with a single compute die and 288 MB for those with two compute dies. Intel already employs bLLC in its "Clearwater Forest" server processors as a passive interposer, integrating local cache beneath active tiles. Including this technology in standard gaming chips could significantly enhance performance, positioning them as strong competitors against the upcoming "Zen 6" processor family.
For "Zen 6," AMD plans to place the CPU CCD on TSMC's N2P 2 nm node variant and build the cIOD on the N3P 3 nm node. Additionally, the increased cache capacity will be complemented by advanced x86-64 instruction extensions like AVX512_BMM, AVX512_FP16, AVX_NE_CONVERT, AVX_IFMA, and AVX_VNNI_INT8, among others. This is particularly noteworthy because 16-bit AVX-512 calculations will now be possible on consumer-oriented desktop CPUs, providing an extra performance boost with a fast memory pool nearby.
Source:
HXL on X
This approach is quite similar to Intel's upcoming "Nova Lake" processors, which are also set to receive a substantial boost in cache capacity through the big Last Level Cache (bLLC). Rumors suggest that these will offer 144 MB for SKUs with a single compute die and 288 MB for those with two compute dies. Intel already employs bLLC in its "Clearwater Forest" server processors as a passive interposer, integrating local cache beneath active tiles. Including this technology in standard gaming chips could significantly enhance performance, positioning them as strong competitors against the upcoming "Zen 6" processor family.
77 Comments on AMD "Zen 6" SKUs with 3D V-Cache Could Pack Up to 288 MB of Cache
Another question will be who will have the lower latency cache plus we should be getting higher 1:1 speeds with DDR5 8000 and faster IF speeds on Zen 6 so alot of questions on what performance will look like with the new I/O die. This also means we should finally see a reduction on power consumption at idle on AMD.
I'm looking forward to replacing my 9800X3D with the 12 core single CCD X3D variant when its released.
After reading the headline 3 times and the text I clicked on teh source. The source was Twitter with 2 simple lines and no real new information.
Those will also be halo products, and many folks will buy them for that reason. A great example of that are the folks that bought a 9950x3D just for games instead of the similarly performing 9800x3D for said use case.
Btw a single CCD 12 core CPU is rumoured, could it feature 216 MB of 3D V-Cache?
Has the article acknowledged him?
www.techpowerup.com/review/intel-core-ultra-7-265k/24.html
Although you'd really like to see lower idle numbers than 50w on desktop in general. It can be hard though when the chipset takes 7-9w by itself.