NVIDIA is reportedly experiencing manufacturing issues with its next-generation "Rubin Ultra" GPU design, one of the company's most ambitious chip development projects, due to the limitations of modern packaging technology. The world's largest company is already shipping customer samples of the standard "Rubin" GPUs, with mass shipments set to begin this summer. However, the current roadmap for the upgraded "Rubin Ultra" design may be encountering technological limitations, as NVIDIA's design goals are too ambitious for TSMC's packaging capabilities. Reportedly, NVIDIA plans to double the regular "Rubin" two-die package with 8 HBM4 modules into a new "Rubin Ultra" package that will include four silicon dies and 16 HBM4E modules in a single package. This configuration is scheduled for 2027, but the sheer volume of silicon may be too much for TSMC's packaging, according to Global Semi Research.

In a typical CoWoS package, TSMC usually combines multiple smaller dies and multiple HBM memory modules into a unified package that supports the entire AI build-out. However, with the ambitious "Rubin Ultra" design, NVIDIA planned to use CoWoS-L, which was expected to handle the design and concept that "Rubin Ultra" was based on. It is rumored, however, that in a 2+2 die package—meaning four dies as in this architecture—TSMC is encountering warping issues. The package—which includes a substrate—is bending in multiple directions, causing the compute dies of "Rubin Ultra" to not make complete contact with the underlying substrate. This instability means that TSMC has to explore alternatives within its packaging portfolio. One of these alternatives is a panelized approach called CoPoS, which stands for Chip-on-Panel-on-Substrate.TSMC initially planned to establish CoPoS pilot lines as early as 2026, aiming for mass production between late 2028 and the first half of 2029. This change involves replacing approximately 300 mm silicon interposers with large square and rectangular panels. Early formats measure around 310 × 310 mm, with later options extending to 515 × 510 mm and even 750 × 620 mm. The larger, square format is designed to reduce wasted edge area, accommodate bigger reticles and masks for AI accelerators, and facilitate placing more dies and HBM on a single package. However, it is uncertain if CoPoS will be ready for a 2027 debut or if TSMC will need to address the CoWoS issues first.