Thursday, May 21st 2026
AMD Announces Production Ramp of Next-Generation AMD EPYC Processor "Venice" on TSMC 2nm Process Technology
AMD today announced that its next-generation AMD EPYC processor, codenamed "Venice," is ramping production in Taiwan on TSMC's advanced 2 nm process technology, with future plans to ramp production at TSMC's Arizona fabrication facility. The milestone in the execution of the AMD data center CPU roadmap demonstrates continued progress toward delivering the leadership performance and energy efficiency required for next-generation cloud, enterprise and AI infrastructure. "Venice" is the first high-performance computing (HPC) product in the industry to enter production on TSMC's advanced 2 nm process technology.
"Ramping 'Venice' on TSMC 2 nm process technology marks an important step forward in accelerating the next generation of AI infrastructure," said Dr. Lisa Su, chair and CEO, AMD. "As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster. Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment."
As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure, coordinating data movement, networking, storage, security and system orchestration across the data center. The ramp of "Venice" comes as AMD continues to build momentum in the server market, reflecting growing customer demand for EPYC processors to power modern cloud, enterprise, HPC and AI deployments.
The "Venice" ramp in Taiwan and plans to ramp at TSMC Arizona reflect AMD's focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, AMD is expanding the foundation needed to support customers as they deploy and scale AI infrastructure.
"We are pleased to see AMD continue to make strong progress with its next-generation EPYC processor on our advanced 2 nm process technology," said Dr. C.C. Wei, Chairman and CEO, TSMC. "Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing."
AMD also plans to extend TSMC 2 nm process technology across its data center CPU roadmap with "Verano," a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, "Verano" is expected to build on the AMD EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications.
AMD and TSMC's partnership spans the technologies needed to scale modern data center computing, from TSMC 2 nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC's SoIC -X and CoWoS -L, used across AMD's broader AI and data center portfolio. With "Venice" ramping on TSMC 2 nm, AMD is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC's process and packaging leadership to deliver increasingly integrated compute platforms at scale.
Source:
AMD
"Ramping 'Venice' on TSMC 2 nm process technology marks an important step forward in accelerating the next generation of AI infrastructure," said Dr. Lisa Su, chair and CEO, AMD. "As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster. Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment."
The "Venice" ramp in Taiwan and plans to ramp at TSMC Arizona reflect AMD's focus on strengthening its geographically diverse advanced manufacturing footprint. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, AMD is expanding the foundation needed to support customers as they deploy and scale AI infrastructure.
"We are pleased to see AMD continue to make strong progress with its next-generation EPYC processor on our advanced 2 nm process technology," said Dr. C.C. Wei, Chairman and CEO, TSMC. "Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing."
AMD also plans to extend TSMC 2 nm process technology across its data center CPU roadmap with "Verano," a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, "Verano" is expected to build on the AMD EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth and efficiency required for increasingly power constrained workloads and applications.
AMD and TSMC's partnership spans the technologies needed to scale modern data center computing, from TSMC 2 nm process technology for next-generation CPUs to advanced packaging technologies, including TSMC's SoIC -X and CoWoS -L, used across AMD's broader AI and data center portfolio. With "Venice" ramping on TSMC 2 nm, AMD is advancing the CPU foundation for AI infrastructure while continuing to leverage TSMC's process and packaging leadership to deliver increasingly integrated compute platforms at scale.
18 Comments on AMD Announces Production Ramp of Next-Generation AMD EPYC Processor "Venice" on TSMC 2nm Process Technology
Anyway, is it now possible that we are reaching an apex on how much we can stuff on a die before it becomes pointless and advances will have to come from somewhere else? Maybe.
Also older CPUs might be disappointing for you, but for people who already have an AM4 platform with a Zen2 or older CPU model, it's an option. For people with spare DDR4, it's an option. For people who don't want to pay for DDR5, it's also an option.
that was Zen 5
I can't really fault AMD for making server parts a priority, that IS where the $ are, not to mention that they got a TON of orders already for them, so it's a very stable market for them
The current desktop market is super unstable because of everything else is much more expensive than in the past
Currently, Intel still holds majority of server CPU's shipped, but AMD is climbing pretty fast (2-3% per year on average). And so does ARM.
The thing is, AMD shipped maybe half od chips than Intel last time, but revenue of AMD was comparable to Intel's. (AMD 46%, Intel 54%).
That means Intel sells more less expensive chips and AMD sells less more expensive chips.
Gemini AI predicts ARM will disrupt server CPU market so much that in 2030 it will hold majority of market share (currently it's around 17%).
By the same time AMD and Intel will be roughly 1:1 in terms of shipped units but AMD's revenue will prevail.
But it might also be completely different, meaning AMD and ARM-based CPU makers rely heavily on TSMC, Intel has it's own fab now.
Intel might allocate majority of production queue for themselves, others might compete for queues in TSMC or in Intel.
We'll see.
Anyway, Zen 3, 4, 5 were designed with server-approach in mind, that's why they're all chiplet-based architectures - universal, modular, scalable. Zen 6 won't be different.
That can read like defending AMD, but the real problem is further upstream. Much like when mining was screwing up the market, the people with means will find a way to secure their orders.
Even considering all that, this practice is nothing new. The best silicon always lands where it gets the highest margins. Binning and volume production ultimately means that Zen6 will eventually find its way into desktop products.
It has now been a 13mo since 2nm tape out of venice and mi450 is supposed to be on this 2nm node as well.
Competing against Vera-rubin is probably priority #1 for AMD.
Other factors would be... AMD tried a new interconnect tech for Strix-Halo, and I don't think it worked as well as they would hope and cost a lot more.
The desktop dual chiplet designs are IF and memory constrained, there are rumors Zen6 IOD has a dual memory controller allowing quad or dual channel depending on the board.
I want new products, I don't want to wait for grok to eat first... but I also don't want half baked products.
chipsandcheese.com/p/strix-halos-memory-subsystem-tackling
I think its good for try 1, but it might not be good enough for zen6 and increases in latency for a better fabric are typically not desired/expected.
Given how delayed strix halo was, the fabric for zen6 consumer might be slowing it up.I hadn't seen recent rumors on it, it seems it has coalesced to 2 camps, as you say 2 single channel controllers and 2 dual channel controllers with the caveat that only 1 of those dual controllers can be active at a time due to am5 being dual channel. 1 is a 1 dimm per channel controller tuned for high clock, the other is a 2dpc channel controller for dual channel.
I look forward to official statements as to what they decided... sad that the jerry rig quad channel on am5 rumors seem to have died down.
16 core are memory constrained 24 surely will be as well... and the gap to threadripper and epyc is rather vast.
They need to bring out a mid-tier on SP6 or something lol, they just brought 84 zen5 cores to it, and its power capped at a more reasonable level.