Sol_BadguyBro you got your wish, AVX-512 instructions.

Good news. MAybe we get finally AVX512 support and usage in Microslop w11 pro, etc. When windows can be installed and run on intel 3rd / 4th core generation the higher cpu instructions are hardly in use. AFAIK we are at intel 16th core cpu generation (feel free to check yourself and continue to count)

I wrote about that for years. My code does not execute on intel, it will crash.

from this text here:

without which thread migration between the two core types will result in runtime errors arising from ISA mismatch.

I need to finish building my second am5 box.

I have another computer to build in the future to replace a ryzen 5800x, x570 box. Intel may be interesting to that person with the use case microsoft windows only with high performance. Intel was ruled out at that time. On a second thought, 420Watt claim for the future intel platform makes it a red flag again. I expect better energy efficiency for those P cores and other cores as any Ryzen 7000 or ryzen 9000 cpu cores. That also includes time used for certain tasks for amd processor x vs intel processor y where the intel processor needs to be 20% or higher more energy effiicent. That means 20% less energy usage. Anything below is not noticeable and not worth considering.

I see it very positive news, intel sticks to common avx512 standards.

Intel needs to gain trust in its manufacturing and engineering department:
I do not trust intel as AX210 (lying around has cost me around 40 € and is defective), also another AX200 wlan chip were faulty, ethernet chips were faulty and intel 13th and 14th core chips were faulty. my previous refurbished notebook had an intel sata ssd where lenovo stated malware inside. I found that only by chance as i looked it up.
I value INTEL Desktop graphic cards better as at the release date. Bringing not the next generation to the market is a negative point and that causes a long term do not buy flag for intel desktop graphic cards.

--

What i see over years, in the linux kernel changes, i talk about the kernel and not the operating system!, those p and e cores are poorly supported. When i see a few weeks ago still code put in the scheduler which is a very important part of the kernel on how to divide the workload it indicates since the intel 12th generation there is hardly any software support.

I repeat also another statement, not every software is multi core capeable.
I had to enable on my gnu gentoo linux only for a 8 core ryzen 7700x parallel compilation and installation protocol, as the cpu idles. Even 8 cores are not utilised properly these days with the gnu toolchain. of course i am aware of the "make --jobs 16" feature, to generate 16 compile jobs for e.g. building the kernel. Still the installation phase seems to be single core only.

When you are encoding videos which should be done on the graphic card and not on the cpu, a layer 8 error, you may need such high core intel cpus with lower cpu instructions. 100% agree, nothing to discuss about. I hardly ever had the need to reencode videos etc. since i own a computer or used a computer since 1989.

ncrsOr rather since Nova Lake was confirmed to feature AVX10. AVX10 is fully backwards compatible with most of AVX-512 (it's missing deprecated Xeon Phi parts) so we get AVX-512 on E-cores, but in fact we get much more with AVX10 and APX.

We had that argumetn already. Than someone else pulled a spec sheet. And i pulled a spec sheet. Than we discussed here, i pulled an older spec sheet, that user pulled a newre spec sheet.

intel can not be trusted on the avx10.x statement, as intel changed it at least once.
I did download both spec sheets and compared it in split view, line per line on the important stuff.
When it is really AVX512, than Intel should name it AVX512. I expect common names to be used.

I did not bought ryzen 9000 cpu, as in my personal use case study on my gnu gentoo linux box, only a few packages used it. I do not remember anymore, was it 10 or 20 packages which used avx512 in around 1300 installed packages. Therefore if it needs two times on a ryzen 7700x vs the newer ryzen 9700x did not justify to buy a ryzen 9700x. Having an 8 core was an argumeng, having no x3d cache was an argument and having avx512 was an argument.

not every software scales for the big x3d cache. i do overspec my boxes with the cpus and dram, my personal fault. i saw it 2023 when i downgraded the 5800x and used a ryzen 3 3100 cpu for a few months. even that ryzen 3 3100 cpu was very powerful

I had the argument in the past. When it is AVX512 than name it AVX512. When you use a different name than it is something else. Why should someone name it differently. What i remember from several months ago was, Intel uses smaller sizes, it is not 512, it is 256, with the option, not gurantee size of 512.

CPu instructions are important, I saw that myself when i switched over from intel i7-3610qm to the 5800x.

-- intel cpus were not backward compatible, as intel 12th gen lost avx512. I wrote it several times, amd lost XOP instructions and a few ohter instructions were also lost on other cpus which i forgot by now. Luckily xop was only on the amd bulldozer plattform.

Tek-CheckThey are working on unified core already. Most likely after Hammer Lake, post-1954 socket.

Yeah I know about that. I just wonder if the ecore is the training ground for the new core. Its hard to develop a new core in a single gen so the companies generally nibble around the edges. Developing more die efficient core on the side while keeping the ol' reliable around for several generations does make sense. Though I imagine we'll probably still see some form of big.little, to scale up frequency, similar to what amd is doing, just with small cores scaled up rather than big cores scaled down. But just a guess.

N/AI could shave off 1-2 minutes in realityscan but no amount of free gifts can overcome the prohibitive DDR5 tax.

Yep, you and practically every other sane person is hoping for the bubble to pop sooner rather than later... the prices are horrific.

qcmadnessI would expect e-cores to have 2-3 256-bit FPUs while p-cores to have 1-2 512-bit FPUs.

Current Skymont E core has 4x128-bit FPUs that are symmetrical, which was 2x-128 bit in the predecessor. Arctic Wolf in Novalake will likely go 4x-256-bit. Any other config(unless they go with the super wasteful 4x512) will be a downgrade for older and numerous applications.

They way they did that in Skymont benefitted every application without a recompile of any sort.

iameatingjamYeah I know about that. I just wonder if the ecore is the training ground for the new core. Its hard to develop a new core in a single gen so the companies generally nibble around the edges. Developing more die efficient core on the side while keeping the ol' reliable around for several generations does make sense. Though I imagine we'll probably still see some form of big.little, to scale up frequency, similar to what amd is doing, just with small cores scaled up rather than big cores scaled down. But just a guess.

The head architect of x86 is the E core architect, Stephen Robinson.

Both the P core team and the design has been very rusty for a decade now. They called Core a combo of Netburst + Pentium M, when mostly it was Pentium M. I expect that to happen again with only bits of P-core being used in Unified Core with the lineage being the E core.

DavidC1Both the P core team and the design has been very rusty for a decade now. They called Core a combo of Netburst + Pentium M, when mostly it was Pentium M. I expect that to happen again with only bits of P-core being used in Unified Core with the lineage being the E core.

Precisely. E core team has been gaining momentum. This is clearly visible in Xeons. They know that P cores are bloated and need to be retired at some point. However..., SMT is coming back with Coral Rapids, so everything is in the game for a few good years.

GrimlingIs there any practical use of the AVX-512 other than ycruncher?

7zip, video encoding and encryption (used for network traffic) to mention a few.
For more server related workloads there are also RAID, databases, etc. which gains lots of performance from optimizations, not to mention all those "AI" workloads.

XeonsNOpteronsThere are legitimate difficulties with coding for AVX-512 as you need to essentially have your calculations lined up neatly so they can feed into the wider bus of AVX-512. Otherwise, you are just not taking advatange of the larger throughput. But, unfortunately, part of the reason developers do not code for it is laziness and the misconception it is more power hungry for their calculations. Maybe now that both Intel and AMD mainstream CPUs support AVX-512 they will forgo their laziness.

Generally speaking, most instances where SIMD is heavily used, it's working on data vectors way longer than 256 bit, so it's usually just a matter of adjusting the instructions and the loop. There are however exceptions where some SIMD instructions are sprinkled within algorithms that don't work on wide data vectors which fits more along the lines of what you're talking of. AVX-512 and AVX-10.2 also adds new capabilities, so obviously there are new cases where optimizing algorithms for AVX-512/10.2 makes sense where AVX2/AVX/SSE did not.

The slow adoption rate is probably a combination of the misconception you've mentioned and the low adoption rate in hardware. But even AMD's initial double-pumped approach changed that quickly.

Tek-CheckThey are working on unified core already. Most likely after Hammer Lake, post-1954 socket.

I don't think they've ever said that, what we got is a job posting mentioning a "Unified Core team", whatever that means. It seems like everyone jumped to the conclusion that all the CPUs will have only one type of core, even though that name may have nothing to do with that.

I believe it's more likely that different core types becomes variants of the same underlying design, kind of like Zen 5 vs. Zen 5c, but with different feature sets. Hopefully that would mean putting some even bigger P-cores in workstation CPUs etc.

efikkan7zip, video encoding and encryption (used for network traffic) to mention a few.
For more server related workloads there are also RAID, databases, etc. which gains lots of performance from optimizations, not to mention all those "AI" workloads.


Generally speaking, most instances where SIMD is heavily used, it's working on data vectors way longer than 256 bit, so it's usually just a matter of adjusting the instructions and the loop. There are however exceptions where some SIMD instructions are sprinkled within algorithms that don't work on wide data vectors which fits more along the lines of what you're talking of. AVX-512 and AVX-10.2 also adds new capabilities, so obviously there are new cases where optimizing algorithms for AVX-512/10.2 makes sense where AVX2/AVX/SSE did not.

The slow adoption rate is probably a combination of the misconception you've mentioned and the low adoption rate in hardware. But even AMD's initial double-pumped approach changed that quickly.


I don't think they've ever said that, what we got is a job posting mentioning a "Unified Core team", whatever that means. It seems like everyone jumped to the conclusion that all the CPUs will have only one type of core, even though that name may have nothing to do with that.

I believe it's more likely that different core types becomes variants of the same underlying design, kind of like Zen 5 vs. Zen 5c, but with different feature sets. Hopefully that would mean putting some even bigger P-cores in workstation CPUs etc.

There are at least 4 variants of Zen 5.

efikkanI believe it's more likely that different core types becomes variants of the same underlying design, kind of like Zen 5 vs. Zen 5c, but with different feature sets.

Yep. That's it.

qcmadnessI would expect e-cores to have 2-3 256-bit FPUs while p-cores to have 1-2 512-bit FPUs.

I hope you do realize that Zen5 has 4 AVX-512 ALUs (more precisely: 4 execution pipes) and can run 4 AVX-512 instructions in a single clock cycle (that's 2048 output-bits per clock cycle).

For example, the following assembly code runs at 6 instructions-per-clock on Ryzen 9000 CPUs:

.p2align 6
1:
vmulps %zmm28, %zmm29, %zmm0
vmulps %zmm30, %zmm31, %zmm1
vaddps %zmm28, %zmm29, %zmm2
vaddps %zmm30, %zmm31, %zmm3
dec %rax
jnz 1b

efikkan7zip, video encoding and encryption (used for network traffic) to mention a few.
For more server related workloads there are also RAID, databases, etc. which gains lots of performance from optimizations, not to mention all those "AI" workloads.

Really? I don't want it anymore. Make it go away. I don't need rpcs3 performance that bad!

EDIT: I guess this is necessary... /s

atomsymbolI hope you do realize that Zen5 has 4 AVX-512 ALUs and can run 4 AVX-512 instructions in a single clock cycle (that's 2048 output-bits per clock cycle).

For example, the following assembly code runs at 6 instructions-per-clock on Ryzen 9000 CPUs:

.p2align 6
1:
vmulps %zmm28, %zmm29, %zmm0
vmulps %zmm30, %zmm31, %zmm1
vaddps %zmm28, %zmm29, %zmm2
vaddps %zmm30, %zmm31, %zmm3
dec %rax
jnz 1b

I do know that.
I am just comparing Intel's own CPU.

qcmadnessI do know that.
I am just comparing Intel's own CPU.

There is no such thing as "1-2 AVX-512 FPUs". All AMD/Intel CPU cores have a single floating-point unit and that single floating-point unit has multiple execution pipes (or execution ports). A particular pipe can execute a particular subset of the AVX-512 instruction set.

Edit: Replaced "ALU" with "execution pipe".

atomsymbolZen5 has 4 AVX-512 ALUs and can run 4 AVX-512 instructions in a single clock cycle

That's not entirely true. Zen5 has 2x full blown 512-bit ALUs, and 2x 512-bit FADD units.
You can achieve 4 ops/cycle when combining these (like in your example), but it'd important to make the distinction.

iameatingjamReally? I don't want it anymore. Make it go away. I don't need rpcs3 performance that bad!

As an alternative to what? Implementing all relevant ASICs in hardware like Apple does to make it obsolete very quickly?
No thanks, I rather have lots of generic performance which can be used for any algorithm. And if you think just throwing more cores at it is better, remember that ILP + SIMD is usually laying the ground work to even scale further with more cores.

Any Alder Lake, Raptor Lake or Arrow Lake CPUs already have full AVX-512 in their P-cores, it's just disabled. Like your 14700KF/12100 CPUs.

igormpThat's not entirely true. Zen5 has 2x full blown 512-bit ALUs, and 2x 512-bit FADD units.
You can achieve 4 ops/cycle when combining these (like in your example), but it'd important to make the distinction.

If Zen5 had "2x full blown 512-bit ALUs" then it would be able to execute 4*VADDPS per clock cycle, which isn't the case (Zen5 can execute at most 2*VADDPS per clock cycle).

I suggest we use the following terminology: The FPU has multiple execution pipes (or execution ports). A particular pipe can execute a particular subset of the AVX-512 instruction set.

Sol_BadguyRPCS3:
www.techpowerup.com/review/amd-ryzen-9-9950x3d2-dual-edition/8.html
And Linux stuff:
www.phoronix.com/review/amd-zen5-avx-512-9950x

This.

RPCS3 is my primary use of AVX 512 on my machine.

atomsymbolI hope you do realize that Zen5 has 4 AVX-512 ALUs (more precisely: 4 execution pipes) and can run 4 AVX-512 instructions in a single clock cycle (that's 2048 output-bits per clock cycle).

For example, the following assembly code runs at 6 instructions-per-clock on Ryzen 9000 CPUs:

.p2align 6
1:
vmulps %zmm28, %zmm29, %zmm0
vmulps %zmm30, %zmm31, %zmm1
vaddps %zmm28, %zmm29, %zmm2
vaddps %zmm30, %zmm31, %zmm3
dec %rax
jnz 1b

I am doubtful Zen 5 has 4 AVX-512 units per core. Considering Intel has superior per core performance and has "only" two AVX-512 units. Though, this may just be confusion on my part with the terms as I refer to FMA units for Intel cores. I am not sure how many ALUs Intel cores have.

atomsymbolIf Zen5 had "2x full blown 512-bit ALUs" then it would be able to execute 4*VADDPS per clock cycle, which isn't the case (Zen5 can execute at most 2*VADDPS per clock cycle).

My bad on that, I just went from C&C diagram when referring to it:

chipsandcheese.com/p/amds-ryzen-9950x-zen-5-on-desktop

Whereas on AMD's own slides those are labeled as FMA/FMUL units instead of FMA/ALU:


According to Agner Fog, Zen 5 can do lots of INTEGER vector arithmetics at a rate of 4ops/cycle, even when operating with 512-bit registers:

www.agner.org/optimize/instruction_tables.pdf
(pages 150 & 151)

But if we look at the float ops (page 155), then the throughput is indeed halved:


Nonetheless, others have already looked into Zen 5's capabilities, like that really post from y-cruncher's creator:
www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/#port_limit

efikkanAs an alternative to what? Implementing all relevant ASICs in hardware like Apple does to make it obsolete very quickly?
No thanks, I rather have lots of generic performance which can be used for any algorithm. And if you think just throwing more cores at it is better, remember that ILP + SIMD is usually laying the ground work to even scale further with more cores.

Any Alder Lake, Raptor Lake or Arrow Lake CPUs already have full AVX-512 in their P-cores, it's just disabled. Like your 14700KF/12100 CPUs.

I wasn't being serious.....

GrimlingIs there any practical use of the AVX-512 other than ycruncher?

Waves audio plug-ins, R statistical software, anything that uses Intel OneAPI MKL or recent OpenBLAS and runs on an Intel processor.

Anyone know if all the cores on nova lake have the same cache and bandwidth to the bigger lv3 cache?

_roman_We had that argumetn already. Than someone else pulled a spec sheet. And i pulled a spec sheet. Than we discussed here, i pulled an older spec sheet, that user pulled a newre spec sheet.

intel can not be trusted on the avx10.x statement, as intel changed it at least once.
I did download both spec sheets and compared it in split view, line per line on the important stuff.
When it is really AVX512, than Intel should name it AVX512. I expect common names to be used.

I did not bought ryzen 9000 cpu, as in my personal use case study on my gnu gentoo linux box, only a few packages used it. I do not remember anymore, was it 10 or 20 packages which used avx512 in around 1300 installed packages. Therefore if it needs two times on a ryzen 7700x vs the newer ryzen 9700x did not justify to buy a ryzen 9700x. Having an 8 core was an argumeng, having no x3d cache was an argument and having avx512 was an argument.

not every software scales for the big x3d cache. i do overspec my boxes with the cpus and dram, my personal fault. i saw it 2023 when i downgraded the 5800x and used a ryzen 3 3100 cpu for a few months. even that ryzen 3 3100 cpu was very powerful

I had the argument in the past. When it is AVX512 than name it AVX512. When you use a different name than it is something else. Why should someone name it differently. What i remember from several months ago was, Intel uses smaller sizes, it is not 512, it is 256, with the option, not gurantee size of 512.

CPu instructions are important, I saw that myself when i switched over from intel i7-3610qm to the 5800x.

-- intel cpus were not backward compatible, as intel 12th gen lost avx512. I wrote it several times, amd lost XOP instructions and a few ohter instructions were also lost on other cpus which i forgot by now. Luckily xop was only on the amd bulldozer plattform.

Yes, we had and I still don't understand what you are trying to argue.
AVX10.2 is fully compatible with AVX-512 software because it exposes every supported subset of AVX-512. From software perspective an AVX10.2 CPU supports AVX-512 natively as indicated by AVX-512 CPUID bits. That is explicitly stated in the whitepaper.
No need to download old versions of the specs - they are all available on Intel's site and they have embedded change logs. The latest version is the valid one and what is to be expected with Diamond Rapids/Nova Lake. The latest version has 256bit-only cores removed, so all cores will be 512-bit. What remains to be seen is whether E-cores have hardware 512-bit widths or will do 2x256-bit like Zen 4. That is an implementation detail with no visibility to software.

Finally, the oncoming competition from Nvidia with its ARM APUs featuring 2048-bit SVE is stimulating AMD and Intel into action...

GrimlingIs there any practical use of the AVX-512 other than ycruncher?

When utilized properly, you gain a massive performance boost and lowers power consumption. You heard right, more power efficient. For example, FFMPEG saw a 100x speed improvement by utilizing AVX-512. AVX-512 Optimization For Linux RAID Showing Up To 41% Improvement On AMD Ryzen 9 9950X. You tend to see more of this on Linux than on Windows since distros are now coming with pre-compiled binaries that make use of AVX-512. It's not the same as what FFMPEG and RPCS3 have gotten out of AVX-512, since you're setting the compiler to make use of it, which hardly makes a difference. You gotta go back and hand optimize the code to see the massive gains.

It was kind of funny how intel dropped avx512 just when it was gaining traction. Good that they enable it again.