Thursday, July 9th 2026
AMD Confirms EPYC "Venice" Zen 6 CPUs Launch on July 22-23 at Advancing AI Event
AMD CTO Mark Papermaster has confirmed that EPYC "Venice," the company's first Zen 6 server CPU, will be officially introduced at AMD's Advancing AI event on July 22nd and 23rd. In a recent interview, Papermaster described the upcoming CPUs as optimized for traditional x86 enterprise workloads, noting that enterprise customers aren't moving away from x86. EPYC "Venice" is built on TSMC's 2 nm process, making it the first high-performance computing processor to reach production on that node. Currently, manufacturing is ramping in Taiwan, as AMD announced back in May, with future production planned at TSMC's Arizona facility. The flagship configuration goes up to 256 Zen 6 cores, a 33% jump over the current 192-core EPYC "Turin" lineup. AMD claims over 70% higher performance and efficiency compared to the Zen 5-based predecessor.
On the platform side, "Venice" moves to the new SP7 socket with 16-channel memory support delivering up to 1.6 TB/s of bandwidth, and adopts PCIe Gen 6 for improved CPU-to-GPU communication. This is mostly relevant for the AI accelerator workloads that the EPYC "Venice" Zen 6 CPUs are targeting alongside traditional x86 tasks. These CPUs when installed in Helios racks, will be paired with new AMD Instinct MI455 GPUs. If you're wondering about the mainstream Zen 6 desktop and mobile chips, those are a separate story. Related to those, there's no shortage of rumors and leaks, whether we are talking about the confirmed Ryzen Threadripper TR6 "Mustang Peak", the Ryzen 10000 series "Olympic Ridge" or the "Medusa Point" APUs. However, consumer parts aren't expected before the end of the year at the earliest, with CES 2027 in January being the most likely debut window.
Sources:
Wccftech, Overclock3d
On the platform side, "Venice" moves to the new SP7 socket with 16-channel memory support delivering up to 1.6 TB/s of bandwidth, and adopts PCIe Gen 6 for improved CPU-to-GPU communication. This is mostly relevant for the AI accelerator workloads that the EPYC "Venice" Zen 6 CPUs are targeting alongside traditional x86 tasks. These CPUs when installed in Helios racks, will be paired with new AMD Instinct MI455 GPUs. If you're wondering about the mainstream Zen 6 desktop and mobile chips, those are a separate story. Related to those, there's no shortage of rumors and leaks, whether we are talking about the confirmed Ryzen Threadripper TR6 "Mustang Peak", the Ryzen 10000 series "Olympic Ridge" or the "Medusa Point" APUs. However, consumer parts aren't expected before the end of the year at the earliest, with CES 2027 in January being the most likely debut window.
AMD's Mark Papermaster - Chief Technology Officer and Executive Vice President"I'll say for me, every enterprise conversation I'm having now, this comes up. Because enterprises have, you know, decades of running x86. They're not going to move that install base. And what we've done at AMD, you know, since we launched the new Zen processor back in 2017. We're now on our sixth generation. So, at our Advancing AI event on July 22nd and 23rd, we're rolling out this new generation. You know, it continues the kind of leadership x86 CPU, but it's designed in such a way that it matches what I just described a moment ago. It's optimized for standalone x86 traditional workloads."
36 Comments on AMD Confirms EPYC "Venice" Zen 6 CPUs Launch on July 22-23 at Advancing AI Event
If they were smart, they wouldn't charge more than the current Epyc flagship, since it requires a new socket
I'll wait on ebay for a good deal.
I have the feeling my lying around ryzen 7600x clocks much better as it has 2 defective cores vs the ryzen 7700x I bought. I assume, I'm certain AMD put the good silicon on the server parts and the e-waste ones on the consumer front.
Do not worry your E-waste will arrive later on the desktop. E-waste in regards of the quality of the yield of the wafer
Only time will tell. Anyway AMD needs a way to get rid of the bad performing cores and the cores with partly defects
MAybe we will get more cpu instructions because of the "AI" whatever feature inside.
I'm assuming 1H 2027 launch for Zen 6 Desktop.
Zen6 EPYC is said to run MRDIMMs at up to 12,800 MT/s, but that's a completely different memory configuration for servers. Normal DIMMs could run up to around ~8000 MT/s
Prices are going to be brutal the first months
So your metric is higher clock? That's it?
My metric is power efficiency, cpu instructions and less compile times. (i am surre that needs to be said in clear text = less!)
Why do server cpu clock with fewer clocks? How many cores? (i do not need an answer for that, these are question to comprehend the topic for those upvoters)
I highly doubt Server CPUS and Desktop CPUs will not be again build on the same building blocks. that is a monetary and yield per wafer decision.
I said it's a stupid thing to claim that desktop parts would get what you called "e-waste". Pure and generic nonsense. Meaningless idea. A bad tech joke.
I did a double take to make sure I read it correctly.
Maybe DFI can make some UV reactive boards for the “new Venice”.
In some situations It’s going to be annoying when searching for specifics even when adding EPYC or Athlon to the search terms.
When Google searching “AMD Athlon Venice” for example, I’m already seeing results for Zen6/EPYC within the top 10 results.
It will just end up getting worse as more info, posts, benchmarks, etc, become available.
Sure, you can change terms and work around it.
Would just be nice if it was actually a completely unique codename.