Friday, August 14th 2026
NVIDIA Secures TSMC A16 Node for Next-Generation "Feynman" GPUs
According to supply chain sources and those close to TSMC, NVIDIA is already working on prototyping the replacement for its "Rubin" and "Rubin Ultra" GPU designs with the next-generation "Feynman" GPU microarchitecture. As noted in the latest report from DigiTimes, NVIDIA is opting for TSMC's A16 node, bypassing the N2 family of nodes entirely in favor of the more advanced 1.6 nm A16 design. Mass production is scheduled for the second half of 2028. The "Feynman" designs will rely on the backside power delivery in the A16 node, as well as on packaging technologies like 3D chiplets using SoIC, CoWoS-L 2.5D integration, and next-generation panel-level packaging.
Initially, NVIDIA will use SoIC 3D stacking technology to stack multiple chiplets into a single package, which will shorten the travel time between chips and reduce latency. These 3D chips will then be packaged side-by-side in a CoWoS-L or CoPoS packaging, creating a multi-kilowatt design capable of processing dozens of PetaFLOPS. For memory, NVIDIA will work with its partners to develop customized HBM, likely HBM4E, by the time "Feynman" reaches mass production. This customized memory includes a specialized base die that can contain logic elements like a memory controller or packet processing unit. Think of it as a way to pre-process data before it enters memory, or as a simple speedup, depending on what NVIDIA aims to achieve.The final piece of the puzzle will be co-packaged optics (CPO), where NVIDIA will introduce optical interconnects between GPUs to reduce latency and power requirements imposed by traditional copper connections. The current "Blackwell" NVL72 rack has a total bandwidth of 130 TB/s between GPUs. "Rubin" doubles that to 260 TB/s, while "Rubin Ultra" also doubles the total bandwidth to 520 TB/s. For "Feynman," the only way to increase system performance is to implement CPO and harness the speed of light to deliver over 1,000 TB/s total system bandwidth, breaking into the petabyte range. All of this will be achieved using TSMC's COUPE technology.
Source:
DigiTimes
Initially, NVIDIA will use SoIC 3D stacking technology to stack multiple chiplets into a single package, which will shorten the travel time between chips and reduce latency. These 3D chips will then be packaged side-by-side in a CoWoS-L or CoPoS packaging, creating a multi-kilowatt design capable of processing dozens of PetaFLOPS. For memory, NVIDIA will work with its partners to develop customized HBM, likely HBM4E, by the time "Feynman" reaches mass production. This customized memory includes a specialized base die that can contain logic elements like a memory controller or packet processing unit. Think of it as a way to pre-process data before it enters memory, or as a simple speedup, depending on what NVIDIA aims to achieve.The final piece of the puzzle will be co-packaged optics (CPO), where NVIDIA will introduce optical interconnects between GPUs to reduce latency and power requirements imposed by traditional copper connections. The current "Blackwell" NVL72 rack has a total bandwidth of 130 TB/s between GPUs. "Rubin" doubles that to 260 TB/s, while "Rubin Ultra" also doubles the total bandwidth to 520 TB/s. For "Feynman," the only way to increase system performance is to implement CPO and harness the speed of light to deliver over 1,000 TB/s total system bandwidth, breaking into the petabyte range. All of this will be achieved using TSMC's COUPE technology.


10 Comments on NVIDIA Secures TSMC A16 Node for Next-Generation "Feynman" GPUs
I can't wait to see what people will say when the 6x & 7x series of GPU's launch with prices in the $8-15K price ranges, with only 2GB of vram for the base models :D