Intel, in a detailed presentation, detailed the package design of its next-generation Xeon 7 "Diamond Rapids" server processor. The processor is designed to be a versatile serial processing powerhouse for enterprise-scale agentic AI. Intel's design goal with the processor is to offer up to 256 P-cores, cushioned by up to 1.28 GB of last-level cache, per socket. The chip also features contemporary I/O, including PCI-Express Gen 6. Intel is leveraging its latest in-house foundry node, the Intel 18A-P, to design the core complex chiplets.

Xeon 7 "Diamond Rapids" is built on essentially the same disaggregation philosophy as AMD EPYC—that of CPU cores being spun out in small groups of CPU core complexes (CCXs) contained in CPU core dies (CCDs), groups of which interface with a centralized server I/O die (sIOD), which serves as a system agent and I/O hub. The "Diamond Rapids" MCM consists of two Fabric Hub Tiles (FHTs), four CPU core Base Tiles, and a total of 16 core chiplets, each containing 16 "Panther Cove" P-cores. The core-count per compute base tile is 64, and four of these add up to 256 cores.Intel is building each of the 16 core chiplets on its latest Intel 18A-P foundry node. The base tiles that seat these chiplets is built on the Intel 3-T foundry node. Meanwhile, the two Fabric Hub Tiles are built on the Intel 3 foundry node. The processor is hence built entirely on Intel foundry nodes, with no external foundry dependency.

On the compute base tiles, Intel is employing Foveros 3D Direct hybrid bonding interface to interconnect the four core chiplet tiles. The base tile provides high density microscopic wiring that interconnects the four tiles on top, and aggregates their wiring to the Fabric Hub Tiles. The four base tiles are then connected to the Fabric Hub Tiles via substrate copper links that conform to the Intel co-sponsored UCIe-S chiplet interconnect architecture, in a fan-out fabric topology.The base tile is more than just a glorified interposer for the four core chiplets on top, there's a reason the company chose a fairly advanced foundry node such as Intel 3-T for this tile, when most traditional interposers can make do with older, more mature nodes. The core chiplets only contain CPU cores with their dedicated L2 caches, but don't feature shared L3 caches. They instead feature a 3D crossbar (Xbar) which facilitates transfers among the 16 P-cores contained in the core chiplets, and connects them to the base tile.

It is the base tile that contains a last-level cache (LLC) that's shared among the four core chiplets. This way, Intel has been able to achieve LLC pooling among 64 cores. Each base tile features a massive 320 MB L3 cache shared among the four core chiplets. Each of the 16 cores on a core chiplet has equal access to the 320 MB L3 cache located on the base tile. Besides the 320 MB L3 cache, the base tile features a caching agent and snoop filter for the cache, and a die-to-die interconnect that connects the base tile to the Fabric Hub tile.

Intel built the Fabric Hub tile on the Intel 3 foundry node. There are two of these, each connects to four compute base tiles. The Fabric Hub Tiles contain the processor's memory controllers. We know from an older Intel presentation given in June 2026 that each FHT features an 8-channel DDR5 memory interface, and the package hence features a total of 16 DDR5 memory channels. These support 12,800 MT/s MRDIMMs.Each of the two Fabric Hubs puts out 64 PCI-Express Gen 6 lanes, which are configurable as CXL 3.0 lanes, and UPI 3. They also feature eight PCIe Gen 4 lanes for low-level platform connectivity. Intel has also given each of the two Fabric Hubs a full set of fixed-function accelerators, including TDX, SGX, QAT, and DSA.Not much is known about the "Panther Cove" P-cores, but the ISA details put out in this presentation talk about support for Advanced Matrix Extensions (AMX), AVX 10.2, and support for data formats such as FP8, FP16, and BF16.