I don't understand what any of this means except that it'd be nice to be in Prague... Visited last year and stayed in the nicest hotel in my life... food was great too! Found an amazing burger place around the corner... good times

Are they trolling us?? IBS (irritable bowel syndrome) at a "plumbers conference"

DrUsmanSaleemshows whether the data came from DRAM or external memory such as CXL. That matters on tiered-memory servers, where Linux has to find frequently used ("hot") pages on slower CXL memory and move them to DRAM.

So if I'm reading this correctly, there's no gains to be had here for the consumer version of Zen6? Oh well, was hyped for a minute it could boost x3d cache access or something.

It would be awesome to hear of some newer features for consumers as well, but so far all leaks only point towards more cores, IPC and frequencies... nothing conclusive though.

I just wished they'd stop their whole focus on datacenter servers... even if only to talk to us consumers, for 5minutes or so.

BeertintedgogglesAre they trolling us?? IBS (irritable bowel syndrome) at a "plumbers conference"

Wow, quite the coincidence. :laugh:

Its a way to put memory thats slower to use on a PCIe card and have less cost in these insane days.

JyubeiSo if I'm reading this correctly, there's no gains to be had here for the consumer version of Zen6? Oh well, was hyped for a minute it could boost x3d cache access or something.

From what I am reading, a same same old 6nm I/O Die is en route to be used on Zen6, but the improvement here will be higher fclocks to solve the bandwidth starvation on AMD chips, this will allow higher throughout everywhere, and as far as I know, the I/O Die may be using old process tech, but there are substantial improvements under the hood for the interconnect fabric that links the I/O dies to the CCD's.

All good

I'm waiting on openSIL bios and cheaper ram prices.

So the gist is that processors execute as many as 400 instructions at the same time (for various definitions of "at the same time"). This makes traditional profiling difficult, as what does "instruction pointer" really mean when CPUs execute multiple instructions at the same time (superscalar), and out-of-order ??

Intel has a more traditional solution where they worked very hard on associating which instruction + pipeline is associated with which memory addresses. (www.intel.com/content/www/us/en/developer/articles/tool/performance-counter-monitor.html specifically their "PEBS" feature).

AMD did a different approach. AMD leaves their own "traditional profiler" somewhat inaccurate: it basically doesn't know which instruction is "executing right now". Instead, AMD has a 2nd mode called "instruction based sampling", where whenever the "profiler" has been triggered, the processor will collect all the statistics on a singular instruction.

IBS is a bit of an inversion on the traditional profiling / hardware performance counters. So it takes some getting used to / thinking to yourself, and chewing on the concepts. But good information can still be gleaned. In particular, this leads to incredible information about how long a specific instruction sat in the retirement queue, in decoding, or waiting for L1, L2, or L3 memory. It seems like Zen6 extends this to include more information on CXL / memory waits across the infinity fabric. A natural extension but a welcome new tidbit of information for anyone studying high-performance code on CPUs, and Zen processors in particular.

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IMO, you either "know" about IBS, or you don't know (and don't care). Its a niche subject, but tracking the exact number of cycles instructions take in every "zone" of a processor (decoding, pipelines, stalls, and retirement) is good information!

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As far as an optimizer that's always listening and thinking about how to move pages around more optimally... well... multithreaded programming is hard, local memory vs remote memory is harder, and automatic optimization of these things is hardest. So I'm not too surprised to see mixed results here.

RootinTootinPootinFrom what I am reading, a same same old 6nm I/O Die is en route to be used on Zen6

I have heard zen6 should come with a new 3nm I/O Die?
Would be very disappointing to have the old old 6nm one from zen4 being recycled for the second time!

RootinTootinPootinFrom what I am reading, a same same old 6nm I/O Die is en route to be used on Zen6, but the improvement here will be higher fclocks to solve the bandwidth starvation on AMD chips, this will allow higher throughout everywhere, and as far as I know, the I/O Die may be using old process tech, but there are substantial improvements under the hood for the interconnect fabric that links the I/O dies to the CCD's.

I thought rumors were saying the I/O die was going to be on a improved process not still on 6nm. As they still need to address idle power usage!

MakaveliI thought rumors were saying the I/O die was going to be on a improved process not still on 6nm. As they still need to address idle power usage!

nahh, same node but under the hood fixes and enhancement, though its not sure how high the FClock can go this time, I don't have my hopes high for that..