Tuesday, October 13th 2026
AMD Showcases Its Next-Gen EPYC "Verano" CPU, Up to 192 Cores and LPDDR5X Memory
AMD showed off its next-generation EPYC "Verano" server CPUs during CEO Dr. Lisa Su opening keynote at the 2026 OCP Global Summit. The new CPU is the first EPYC processor to support LPDDR5X memory via SOCAMM2 modules. Now AMD is mirroring rival NVIDIA's Vera CPU that already uses SOCAMM2 modules. The "Verano" processor sits within the EPYC 9006 "LP" family and is built on the same TSMC 2 nm process as the already-launched EPYC "Venice". While AMD "Venice" is the first EPYC processor based on Zen 6 architecture, "Verano" is optimized for AI tasks in agentic AI racks. For this, AMD plans to pair them with its own Instinct MI500 GPUs via xGMI connectivity at up to 112 Gbps. It will run on the new SP8 platform rather than Venice's SP7. When we first heard about "Verano", AMD indicated that the upcoming CPUs will feature up to 72 cores on a single-socket platform. However, that has now been updated to up to 192 cores.
From the initial information available, this could mean either a single large chip or a dual 96-core configuration. More details came from System360Cheese on X, who reported that the chip shown featured eight Zen 6 CCDs alongside two large IO dies and four LPDDR5X memory controllers. The CCDs appear smaller than those in Venice's Zen 6C design, suggesting these are the standard 12-core Zen 6 dies rather than the denser 32-core Zen 6C variants. The announcement follows AMD's earlier reveal of the Helion agentic AI rack, an Open Compute Project spec-designed system that Verano is expected to be integrated. Availability is targeted for 2027.
Sources:
AMD, Wccftech, System360Cheese on X
From the initial information available, this could mean either a single large chip or a dual 96-core configuration. More details came from System360Cheese on X, who reported that the chip shown featured eight Zen 6 CCDs alongside two large IO dies and four LPDDR5X memory controllers. The CCDs appear smaller than those in Venice's Zen 6C design, suggesting these are the standard 12-core Zen 6 dies rather than the denser 32-core Zen 6C variants. The announcement follows AMD's earlier reveal of the Helion agentic AI rack, an Open Compute Project spec-designed system that Verano is expected to be integrated. Availability is targeted for 2027.
5 Comments on AMD Showcases Its Next-Gen EPYC "Verano" CPU, Up to 192 Cores and LPDDR5X Memory
192-cores is very impressive for the "small" socket.
Another prossibility is just leaving space on the substrate PCB to put more dies in the future. Coral Rapids-AP is supposed to reach 320-cores, and honestly, looking by the area open on the PCB with Diamond Rapids, Intel could slap another two CBBs in and have a 384-core chip if they wanted, but I assume their IO die is not designed to feed six dies.