X5 338H looking good if its the 12 Xe variant.

So they dropped 2P cores in favor of 2LP cores that are E cores with limited boost to 2.5GHZ? Also the max frequency dropped from 5.4 to 5.1 which will require 6% better IPC for 388H just to not be slower than the 285H.
Not to mention it is only 4P cores for their most premium mobile CPU

What about just 16P cores

Proof for 18A failure

Arrow Lake and Lunar Lake were built on TSMC N3B, which I thought was a density-optimized node and had trouble reaching high frequencies, whereas Panther Lake is built on Intel 18A which I thought was frequency-optimized. And here are the frequency numbers which (if true) serve as evidence against what I thought. Then again, TSMC went to market a year before Arrow Lake; compared to 18A it was a mature node. It's easy to imagine 18A getting to the same frequencies in a year.


Arrow Lake uses Lion Cove and Panther Lake's Cougar Cove cores could easily be 5-10% faster at the same clock speed, and they could be capable of sustaining a higher clock speed for longer or the Darkmont E cores could clock higher than Arrow Lake's Skymont cores, so probably the peak single-thread performance will be around the same as Arrow Lake. Panther has simpler packaging and the models in my table here have the small graphics tile, so I think Panther Lake should be a little cheaper, which would be a win.

Also it appears the best dies are going to the big graphics models. The X9 388H has a peak frequency only 4% lower than the 285H. Considering Cougar Cove is probably that faster at the same frequency, that's a reasonable place to be. AMD has no new chips coming in roughly the next year, so at least Intel's place in the market isn't slipping. (Although Qualcomm might change that.)

Against Lunar Lake, these numbers look better. (Still not apples-to-apples, but Lunar Lake has big graphics so for a handheld this is a sample of what the upgrade path would look like. It's not apples-to-apples because the X9 388H has 8 more cores and 4 more Xe cores and will probably be more expensive. But the graphics tile is made on TSMC N3E, which I believe is quite a bit cheaper than the older N3B Lunar Lake uses, and the off-package memory will also be much cheaper.)

As the Lunar Lake range includes 256 and 288 variants it seems more likely that these 18A Panthers Lake processors with 356 and 388 CPUs are intended to be Lunar Lake replacements. For example both the 288V and 388H have 4 P cores, 4 LPE cores, max turbo speed for both is the same at 5.1 GHz as is memory support at up to LPDDR5X 8533 MT/s. Compared to the 288V the 388H has 4 more E cores for a total of 8 plus the improved iGPU among other changes. The on-package memory feature of Lunar Lake is dropped.

pressing onApart from the 18A node the 388H has 4 additional E cores plus the improved iGPU.

The 388H has eight additional E cores, not four.
Same amount of LPE cores.

You may be thinking of the 338H.

usinameSo they dropped 2P cores in favor of 2LP cores that are E cores with limited boost to 2.5GHZ? Also the max frequency dropped from 5.4 to 5.1 which will require 6% better IPC for 388H just to not be slower than the 285H.
Not to mention it is only 4P cores for their most premium mobile CPU

Panther Lake isn't meant to replace Arrow lake. It's the successotr of lunar lake

pressing onAs the Lunar Lake range includes 256 and 288 variants it seems more likely that these 18A Panthers Lake processors with 356 and 388 CPUs are intended to be Lunar Lake replacements. For example both the 288V and 388H have 4 P cores, 4 LPE cores, max turbo speed for both is the same at 5.1 GHz as is memory support at up to LPDDR5X 8533 MT/s. Compared to the 288V the 388H has 4 more E cores for a total of 8 plus the improved iGPU among other changes. The on-package memory feature of Lunar Lake is dropped.

There is no successor to Lunar Lake and those are in same TDP tier as the normal mobile H, even the names are the same as the mobile H, so those are replacement for 200H. They will be still used in handheld, buy there won't be different SKUs

dyonoctisPanther Lake isn't meant to replace Arrow lake. It's the successotr of lunar lake

If this is the case, their naming and TDP is completely off, not to mention without on board memory, this is not true successor. They can call it whatever they want for marketing, but it won't change the facts

usinameIf this is the case, their naming and TDP is completely off, not to mention without on board memory, this is not true successor. They can call it whatever they want for marketing, but it won't change the facts

Panther lake got more SKUs and core configurations than Arrow Lake (not counting the refreshed Meteor Lake 200 series) , It's covering a wider range of laptops. And It might overlap with a few weaker Arrow Lake laptops. Nova lake H is coming in 2026 too. Panther Lake isn't a main architecture like Arrow lake, it's a bit closer to what Meteor Lake became. MTL and RPL were contemporaneous, with RPL wearing the 200h monikers, when MTL had 100H.

All I can say is that Intel likes to be messy. Be ready to see new premium laptops sporting Arrow Lake refresh, I guess? The X9 can't compete with a mobile HX, so Arrow Lake will still own the performance segment.

IIRC, Intel also announced that the on-package memory thing was a one-off, so they won't ever be a "true" successor to Lunar Lake.

I await to see the benchmarks. I want to see if there's one cpu out of these that can replace the 20 cores 255hX or if Intel will later produce a 368 hX version

I’m eager to read the reviews

Wasn't Lunar Lake capped at 5.1 GHz? And that was 3 nm.
Intel claims Panther Lake has 30% better efficiency.
That means that with same clocks, it should eat much less power. Or not?

www.notebookcheck.net/Benchmark-leak-Intel-Core-Ultra-X7-358H-slower-than-Core-Ultra-7-255H-but-iGPU-impresses.1151346.0.html

It seems they focused mainly on improving the iGPU part. CPU performance does not look to be better than Arrow Lake's H one.
I mean, 5.1 is enough for mobile devices, thought I expected few hundreds of Mhz on top of that due to newer process node.
It's not like Panther Lake's all cores will boost evenly to 5.1 GHz under full load. It's a per core boost limit.
I kind of expected for a single core to have ability to boost a bit higher, even if just for a brief period.

As if the situation wasn't complicated enough for Intel with different architectures for two sets of cores, they implemented 3rd set of cores ...

LittleBroAs if the situation wasn't complicated enough for Intel with different architectures for two sets of cores, they implemented 3rd set of cores ...

Intel has had two types of cores in three types of function for several years.

LPE cores existed in Meteor Lake, in their own low power island, besides that they're identical to E cores. They do their job very well, and Intel U series laptops have excellent battery life due to it.

dgianstefaniIntel has had two types of cores in three types of function for several years.

LPE cores existed in Meteor Lake, in their own low power island, besides that they're identical to E cores. They do their job very well, and Intel U series laptops have excellent battery life due to it.

Sure, but they require even more delicate approach than e-cores. As you wrote, they are physically isolated, they don't have access to L3 cache of compute tile.
Also as you may know that In Meteor Lake and Arrow Lake-H most of tie time LP e-cores are present, but not used (parked). 2 Crestmont LP e-cores were not enough to satisfy performance
demands even for very undemanding tasks, such as running things in background and reading through PDF document.

It has changed with Lunar Lake, when there were no e-cores along with P-cores, but 4 Skymont LP e-cores on low power island and then regular 4 P-cores.
4 Skymont e-cores were finally powerful enough to handle light tasks without unparking P-cores. So, only since Lunar Lake they proved to be actually effective.
What I don't get is why Intel is still using 3 different sets of cores, when P-cores + LPe-cores would be least pain in the ass option and maybe the most effective.
E-cores kind of lose their meaning when Intel continues to improve them nearly to P-core level. E-cores on separate island, on the other hand, allows P-Cores to be switched off,
which introduces significant energy savings, as you wrote. Having two sets of e-cores of same architecture on two different islands is complicated. (And pointless?)
Scaled up Lunar Lake approach would be better solution, IMO. 8 P-cores + 0 e-cores + low power island 8 LP-cores would be amazing.

FoulOnWhiteWhat about just 16P cores

There's no point in making a mobile 16P chip as it will get outperformed by a variant with (LP)E cores in the same power budget.

LittleBroSure, but they require even more delicate approach than e-cores. As you wrote, they are physically isolated, they don't have access to L3 cache of compute tile.
Also as you may know that In Meteor Lake and Arrow Lake-H most of tie time LP e-cores are present, but not used (parked). 2 Crestmont LP e-cores were not enough to satisfy performance
demands even for very undemanding tasks, such as running things in background and reading thought PDF document.

It has changed with Lunar Lake, when there were no e-cores along with P-cores, but 4 Skymont LP e-cores on low power island and then regular 4 P-cores.
4 Skymont e-cores were finally powerful enough to handle light tasks without unparking P-cores. So, only since Lunar Lake they proved to be actually effective.
What I don't get is why Intel is still using 3 different sets of cores, when P-cores + LPe-cores would be least pain in the ass option and maybe the most effective.
E-cores kind of lose their meaning when Intel continues to improve them nearly to P-core level. E-cores on separate island, on the other hand, allows P-Cores to be switched off,
which introduces significant energy savings, as you wrote. Having two sets of e-cores of same architecture on two different islands is complicated. (And pointless?)
Scaled up Lunar Lake approach would be better solution, IMO. 8 P-cores + 0 e-cores + low power island 8 LP-cores would be amazing.

I think Intel sees LPE cores as essential for battery life, and useless otherwise. That's why Arrow Lake-S on desktop doesn't have LPE cores. Apple processors have separate core clusters and I assume smartphone processors do as well, and may be a big part of why those device tend to do so well with battery life. Even Qualcomm's Snapdragon X processor has 3 clusters of Oryon cores, so perhaps it's like the whole thing is nothing but big LPE cores.

Going for just P cores and LPE cores seems like potentially and upgrade over what Qualcomm does, but I suspect it doesn't offer the best potential. AMD has also started to mix big and little cores on mobile. Phoenix 2 started it with 2 Zen 4 cores and 4 Zen 4c cores in the same core cluster, and Strix Point took this idea further with 4 Zen 5 cores and 8 Zen 5c cores in different clusters. So even AMD is combining big and little cores. And it makes sense; AMD and Intel have both said that the little cores are more efficient at lower power; in mobile under a tight power budget the little cores actually make the chip faster than big cores alone. (I also think the Zen 6 successor to Strix Point will move back to 12 cores in one cluster.)

I thought Lunar Lake would have better multithreaded performance than what it ended up delivering. I think Lunar Lake shows that LPE cores can't contribute enough in heavily threaded workloads which seem to want the big L3 cache and fast core-to-core communication. So we have Panther Lake: good battery life is achieved with LPE cores which spend no power on L3 cache or a big ring bus, and performance is achieved with P cores and once they're busy and there's little power left for more, the E cores come into play.

if Panther Lake performances are meant and actually are better than Arrow Lake mobiles conresponding models ... we wiill say Panther Lake is Arrow Lake's successor.
If they are lower we will desume Panther Lake is meant to be Lunar Lake's successor, i.e. it's meant just for lowering as possible the consumptions not for improving the performance at all.

SquaredI think Intel sees LPE cores as essential for battery life, and useless otherwise. That's why Arrow Lake-S on desktop doesn't have LPE cores. Apple processors have separate core clusters and I assume smartphone processors do as well, and may be a big part of why those device tend to do so well with battery life. Even Qualcomm's Snapdragon X processor has 3 clusters of Oryon cores, so perhaps it's like the whole thing is nothing but big LPE cores.

Going for just P cores and LPE cores seems like potentially and upgrade over what Qualcomm does, but I suspect it doesn't offer the best potential. AMD has also started to mix big and little cores on mobile. Phoenix 2 started it with 2 Zen 4 cores and 4 Zen 4c cores in the same core cluster, and Strix Point took this idea further with 4 Zen 5 cores and 8 Zen 5c cores in different clusters. So even AMD is combining big and little cores. And it makes sense; AMD and Intel have both said that the little cores are more efficient at lower power; in mobile under a tight power budget the little cores actually make the chip faster than big cores alone. (I also think the Zen 6 successor to Strix Point will move back to 12 cores in one cluster.)

I thought Lunar Lake would have better multithreaded performance than what it ended up delivering. I think Lunar Lake shows that LPE cores can't contribute enough in heavily threaded workloads which seem to want the big L3 cache and fast core-to-core communication. So we have Panther Lake: good battery life is achieved with LPE cores which spend no power on L3 cache or a big ring bus, and performance is achieved with P cores and once they're busy and there's little power left for more, the E cores come into play.

AMD is not doing the e core or low power thing. Their approach is about sacrificing L3 cache for more cores. Zen4 cores are same as Zen4c. C stands for compact. Difference is between process node and L3 cache. Architecture and IPC is exactly same for c and non-c cores.

LittleBroAMD is not doing the e core or low power thing. Their approach is about sacrificing L3 cache for more cores. Zen4 cores are same as Zen4c. C stands for compact. Difference is between process node and L3 cache. Architecture and IPC is exactly same for c and non-c cores.

"c" stands for cloud. Phoenix 2 has Zen 4 and Zen 4c on the same core cluster using the same L3 cache.

Performance is IPC * frequency; whether a core has lower IPC or lower frequency, it is the same outcome. AMD has stated that the c cores have peak efficiency at a lower frequency than the non-c cores. AMD uses them to include more cores in the same die area and to improve power efficiency when many cores are in use. AMD has used c cores in c-core-only server CPUs, in laptop CPUs alongside regular cores on the same L3 cache, and in laptop CPUs in their own core cluster with less cache. Replace "AMD" with "Intel" and "c core" with "E core" or "LPE core" and the same paragraph would still be true.

LittleBroAMD is not doing the e core or low power thing. Their approach is about sacrificing L3 cache for more cores. Zen4 cores are same as Zen4c. C stands for compact. Difference is between process node and L3 cache. Architecture and IPC is exactly same for c and non-c cores.

Also no 3DVCache through vias on the C cores.

Squared"c" stands for cloud. Phoenix 2 has Zen 4 and Zen 4c on the same core cluster using the same L3 cache.

Performance is IPC * frequency; whether a core has lower IPC or lower frequency, it is the same outcome. AMD has stated that the c cores have peak efficiency at a lower frequency than the non-c cores. AMD uses them to include more cores in the same die area and to improve power efficiency when many cores are in use. AMD has used c cores in c-core-only server CPUs, in laptop CPUs alongside regular cores on the same L3 cache, and in laptop CPUs in their own core cluster with less cache. Replace "AMD" with "Intel" and "c core" with "E core" or "LPE core" and the same paragraph would still be true.

Go find out on the internet what that c letter is for. AMD explicitly stated in their presentation slide.

Compact Zen cores were developed to be applied to servers, where parallelism is of utmost importance. Also power draw is important. That's why they clock compact cores lower - to maximize efficiency. No regular Intel or AMD desktop CPU (except for low power SKUs) are being released with regards to efficiency. Clocks and performance is marketing now. Maybe try to figure out the sweet spot of your CPU.

My 9800X3D is at stock settings rated for 5.25 GHz and 125W TDP. I tried 5.4 GHz and bam, it went to nearly 150W. Then I undervolted and settled for 132W with 5.4 GHz. But temps were above 80s. So I tried 5.1 GHz and undervolt allowed it to run at 104W. I lost negligible amount of performance, but reduced power draw a lot and temps as well. I lost maybe 2% of performance and gained around 25% efficiency. And this is exactly what they do with compact Zen cores - they clock them lower for better efficiency. At server, 25W of TDP translates to 4-5 cores and that's 9-10 threads. Threads are way more important in servers than clocks.

In the end, be it a compact core or non compact one, it IS same damn architecture, with same IPC, same L1 caches, L2 caches, same execution engine. Intel's/Qualcomm's e cores are totally different architecture and on top of that they are optimized for efficiency. Different architectures working jointly mean you require advanced scheduler, as that standard one that OS has is not good enough to handle cores with different IPCs. With AMD's approach you continue to rely on standard OS scheduler, as IPCs of c and non-c cores is same. Clocks are different but clocks don't matter when we're talking about IPC.

See difference now?

We need more "cores" naming diversification... P cores... then E cores... now LPE cores... please add e-waste cores on top of that

LittleBroGo find out on the internet what that c letter is for. AMD explicitly stated in their presentation slide.

"C is for cloud", quoted from this article:
www.hwcooling.net/en/big-little-by-amd-zen-4c-has-the-same-ipc-as-the-big-zen-4-architecture-analysis/

LittleBroCompact Zen cores were developed to be applied to servers, where parallelism is of utmost importance. Also power draw is important. That's why they clock compact cores lower - to maximize efficiency. No regular Intel or AMD desktop CPU (except for low power SKUs) are being released with regards to efficiency. Clocks and performance is marketing now. Maybe try to figure out the sweet spot of your CPU.

My 9800X3D is at stock settings rated for 5.25 GHz and 125W TDP. I tried 5.4 GHz and bam, it went to nearly 150W. Then I undervolted and settled for 132W with 5.4 GHz. But temps were above 80s. So I tried 5.1 GHz and undervolt allowed it to run at 104W. I lost negligible amount of performance, but reduced power draw a lot and temps as well. I lost maybe 2% of performance and gained around 25% efficiency. And this is exactly what they do with compact Zen cores - they clock them lower for better efficiency. At server, 25W of TDP translates to 4-5 cores and that's 9-10 threads. Threads are way more important in servers than clocks.

In the end, be it a compact core or non compact one, it IS same damn architecture, with same IPC, same L1 caches, L2 caches, same execution engine. Intel's/Qualcomm's e cores are totally different architecture and on top of that they are optimized for efficiency. Different architectures working jointly mean you require advanced scheduler, as that standard one that OS has is not good enough to handle cores with different IPCs. With AMD's approach you continue to rely on standard OS scheduler, as IPCs of c and non-c cores is same. Clocks are different but clocks don't matter when we're talking about IPC.

See difference now?

www.tomshardware.com/pc-components/cpus/exclusive-amd-to-begin-disclosing-zen-4c-clock-speeds-and-list-the-missing-core-counts-on-official-spec-pages

Squared"C is for cloud"
www.hwcooling.net/en/big-little-by-amd-zen-4c-has-the-same-ipc-as-the-big-zen-4-architecture-analysis/


www.tomshardware.com/pc-components/dram/high-bandwidth-memory-future-of-ai-one-team-spirit-sk-hynix

"C" is for compact! Not cloud, it's main use has been server to get very high core and thread numbers, but it's also available in mobile to achieve better efficiency without sacrificing core/thread number, i.e. in Hawk Point, Strix Point and others.