Samsung presented its updated memory roadmap at SEMICON Taiwan 2026, with HBM5 and the upcoming zHBM architecture being the main focus points while setting ambitious goals and expectations. According to Samsung, HBM5 is targeting twice the performance and 20% higher performance per watt compared to HBM4E, alongside a 20% reduction in thermal resistance. As changes, the base die moves from the 4 nm process used in HBM4 and HBM4E to Samsung's in-house 2 nm node, and the stack options expand to 12, 16, and 20 layers. Mass production is expected around 2028. Recently, Samsung confirmed at the Hot Chips 2026 conference's Advance Program that the company is preparing to ship HBM4E memory with speeds of 16 Gbps per pin. Samsung is currently shipping HBM4 that works at 11.7 Gbps per pin.

zHBM uses a more radical approach, rather than placing memory beside the accelerator as conventional HBM does, zHBM stacks memory directly on top of the processor, shortening the data path and delivering higher bandwidth and efficiency. With zHBM, Samsung is targeting eight times the raw performance and three times the performance per watt of HBM4E, with thermal resistance reduced by 75-90%. At FMS 2026, Samsung unveiled the industry's first concept models of zHBM and is expected to launch this completely different architecture after 2029. Rethinking the HBM architecture appears to be the direction the industry is heading. NVIDIA recently announced its own NVHBM custom memory that moves the memory controller into the HBM base die rather than keeping it on the compute die.On the NAND side, Samsung is developing zNAND-O, targeted for sampling in 2028. With this, the company is aiming for 10x the bit density of DRAM, 7x the read bandwidth while keeping the power efficiency of conventional NAND. Worth noting that Samsung shouldn't just watch over its rival SK hynix, as China's YMTC giant just announced an ambitious goal of overtaking both Samsung and SK hynix by the end of 2027.

Samsung also outlined its "C.U.B.E" framework at the Memory Executive Summit ahead of the show: four priorities covering Capacity, Utilization, Bandwidth, and Efficiency. The strategy centers on vertical memory expansion to grow capacity without increasing PCB footprint, optimized 3D architecture to reduce latency, vertical high-speed channels to replace horizontal data paths, and a focus on power efficiency and thermal management at the bit level.