Samsung has reportedly booked the entire planned output of its second fab in Taylor, Texas, and most of it is going to AMD. According to an exclusive from Korea's Maeil Business Newspaper, citing industry sources, Taylor Fab 2 will make HBM base dies for AMD and NVIDIA on a 2 nm process, with AMD's orders making up the bulk of it. Apparently, AMD's volume alone is enough to stretch the fab's capacity. Samsung declined to comment, saying it can't confirm customer-related details.

These aren't AMD's CPUs or GPUs, though. The base die is the logic chip at the bottom of an HBM stack, and Samsung plans to pair the Texas-made dies with DRAM produced in South Korea and ship them as finished HBM. Its current HBM4 and the sampled HBM4E use 4 nm base dies, so 2 nm or smaller seems aimed at later HBM generations. The deal also follows Lisa Su's visit to Samsung in October, where Samsung reportedly wanted foundry orders from AMD in return for the HBM that AMD urgently needs. A March MOU had already made Samsung the primary HBM4 supplier for the Instinct MI455X.

Samsung Electronics today reported financial results for the third quarter ended Sept. 30, 2026. The Company posted KRW 195.3 trillion in consolidated revenue, another all-time quarterly high, representing a quarter-on-quarter (QoQ) increase of 14%. Operating profit reached KRW 107.4 trillion, making Samsung Electronics the world's first tech company to exceed KRW 100 trillion in quarterly operating profit.

The Device Solutions (DS) Division posted a QoQ sales increase of 15%, with the Memory Business setting an all-time high for quarterly revenue and operating profit, as semiconductor demand is set to remain robust. The Device eXperience (DX) Division posted a QoQ revenue increase of 8% and recorded an operating loss of KRW 0.8 trillion.

We're excited to introduce Amazon Alexa Tablets—an all-new lineup of tablets that combine powerful hardware, the intelligence of Alexa+, and built-in access to all your favorite apps with Google Play Store. The all-new lineup includes three models: Amazon Alexa Tablet 12 Pro, Amazon Alexa Tablet 11, and Amazon Alexa Tablet 8.

Each new tablet features premium aluminium unibody construction, vivid high-resolution displays, and powerful processors. They seamlessly connect your Amazon experiences right out of the box, run Android, and come with access to the full Google Play Store—millions of apps including YouTube, Netflix, Gmail, and Google Docs, alongside built-in Amazon apps including Prime Video, Kindle, Audible, Amazon Music, Amazon Quick and Amazon Luna.

Samsung's upcoming HBM4E memory has reportedly passed testing for NVIDIA's next-generation "Rubin Ultra" AI GPU accelerator family. This is great news for the company, as its previous HBM3E didn't meet NVIDIA's requirements, leading NVIDIA to choose Samsung for GDDR7 only, instead of HBM3E. The new HBM generation brings significant advancements, and Samsung is one of the leading manufacturers with designs currently running at 14 Gbps per pin and 2,048 pins per HBM4E stack. Samsung can achieve a maximum bandwidth of 3.6 TB/s, and at 16 Gbps, this maximum memory bandwidth will increase to 4 TB/s for a single HBM4E stack.

With about a dozen memory stacks per AI accelerator or GPU, the total memory bandwidth will be remarkable. The company is currently offering this memory in a 12-layer (or 12-high) configuration with a memory density of 48 GB per stack. However, customer requirements will also include 8-layer 32 GB and 16-layer 64 GB stacks in the future.

Samsung is reportedly increasing its orders for materials to boost high-bandwidth memory (HBM) production, with plans to double the production capacity of its current HBM4 and HBM4E manufacturing by 2027. According to SE Daily, the manufacturing capacity for HBM4 and HBM4E is expected to grow from around 20,000 wafers per month in 2026 to 50,000 wafers per month in 2027. This data is derived from the use of glass carriers, which are temporary glass panels placed over thin DRAM wafers to prevent warping or breaking as they are prepared for packaging. Since HBM involves stacking many thin DRAM modules, glass carriers stabilize these wafers until the packaging process begins and the glass is removed. As the unit is one glass carrier per wafer, this provides an estimate of how many HBM4 and HBM4E wafers are produced each month.

Additionally, Samsung's overall HBM production, which includes older generations like HBM3 and HBM3E, currently averages around 180,000 wafers this year and is expected to grow to about 250,000 HBM wafers next year, with 80% dedicated to HBM4 and HBM4E. Samsung began mass production of HBM4 on its sixth-generation 10 nm-class 1c node in February, with HBM4E customer samples available by mid-2026. Future production increases will focus on HBM4 and HBM4E, as customers seek higher densities and bandwidth for their AI accelerators.

According to Korean media, Samsung Foundry, a division that operates silicon manufacturing as a subsidiary of Samsung Electronics, is reportedly allocating significant capacity for HBM4 base die manufacturing. For HBM4, Samsung is producing the base die on a 4 nm node, which reportedly receives half of the entire manufacturing capacity of the 4 nm node, internally referred to as SF4. Customers of HBM4 and the upcoming HBM4E memory standards are now requesting base dies to be filled with custom logic. For instance, customers could implement custom logic like memory controllers and PHYs directly on the HBM base die, significantly reducing the area occupied by these components on the main compute chiplet.

Samsung operates its SF4 manufacturing at Pyeongtaek Campus 2 (P2) and Campus 3 (P3) on lines S5 and S6. An increase in manufacturing is not only coming for ASIC designs by external customers but also for HBM4 base die manufacturing, which is becoming especially important for ASIC customers aiming to maximize the performance of their designs.

Samsung presented its updated memory roadmap at SEMICON Taiwan 2026, with HBM5 and the upcoming zHBM architecture being the main focus points while setting ambitious goals and expectations. According to Samsung, HBM5 is targeting twice the performance and 20% higher performance per watt compared to HBM4E, alongside a 20% reduction in thermal resistance. As changes, the base die moves from the 4 nm process used in HBM4 and HBM4E to Samsung's in-house 2 nm node, and the stack options expand to 12, 16, and 20 layers. Mass production is expected around 2028. Recently, Samsung confirmed at the Hot Chips 2026 conference's Advance Program that the company is preparing to ship HBM4E memory with speeds of 16 Gbps per pin. Samsung is currently shipping HBM4 that works at 11.7 Gbps per pin.

zHBM uses a more radical approach, rather than placing memory beside the accelerator as conventional HBM does, zHBM stacks memory directly on top of the processor, shortening the data path and delivering higher bandwidth and efficiency. With zHBM, Samsung is targeting eight times the raw performance and three times the performance per watt of HBM4E, with thermal resistance reduced by 75-90%. At FMS 2026, Samsung unveiled the industry's first concept models of zHBM and is expected to launch this completely different architecture after 2029. Rethinking the HBM architecture appears to be the direction the industry is heading. NVIDIA recently announced its own NVHBM custom memory that moves the memory controller into the HBM base die rather than keeping it on the compute die.

According to Reuters, Samsung Foundry is experiencing a significant increase in customer orders, prompting the company to adjust its pricing strategy across multiple nodes. In July, Samsung raised the price of its 4 nm node, known as SF4, by about 10-15% for customers in the United States and China, while customers in Taiwan saw a more modest increase of 5-10%. Prices for wafers produced with the 5 nm node, referred to as SF5, also rose by 10-15%. Interestingly, even the older 8 nm node experienced a 10% price hike. This increase for the SF8 node is likely due to NVIDIA placing orders for its GeForce RTX 3060, a product the company has reintroduced after several generations.

There is no mention of price hikes for newer nodes such as Samsung SF2, SF3, and their variations. It seems Samsung anticipated the level of external customer demand for these nodes, and they are already quite costly. Notably, Reuters reports that U.S.-based customers are prioritized after Samsung's internal chip demand for its own SoCs, while China-based design houses are third in line. However, as China seeks advanced nodes, they are willing to accept higher price increases to secure allocation at Samsung Foundry at any cost.

AMD today announced a global launch of the Radeon RX 9070 GRE graphics card. The card was debuted as a China-exclusive, and is seeing a wider launch to fill a key price-performance gap that exists between the RX 9060 XT 16 GB and the RX 9070. The new RX 9070 GRE carved out from the same 4 nm "Navi 48" silicon as the RX 9070 and RX 9070 XT. While the silicon physically has 64 compute units and a 256-bit wide memory bus, the RX 9070 GRE is configured with three quarters of it, featuring 48 compute units, and a 192-bit memory bus. In comparison, the RX 9060 XT and the "Navi 44" silicon it's based on, has exactly half the CU count and memory bus width.

The Radeon RX 9070 GRE hence has 3,072 stream processors, 48 RT accelerators, 96 AI accelerators, 192 TMUs, and 96 ROPs. The card gets 12 GB of 18 Gbps GDDR6 memory across its 192-bit wide memory bus, for 437 GB/s of memory bandwidth. It's also configured with 48 MB of Infinity Cache memory, three quarters of the 64 MB physically present on "Navi 48." The card is configured with 2.20 GHz of Game clock, and 2.79 GHz of maximum boost frequency for the GPU engine clock domain, while the memory ticks at 18 Gbps (GDDR6-effective). The main competition for this card is NVIDIA's GeForce RTX 5060 Ti 16 GB, which is priced at $570. AMD, in its first-party performance tests claims a significant 22% performance gain over the RTX 5060 Ti 16 GB, and a 26% performance-price gain. While NVIDIA recommends the RTX 5060 Ti for 1080p gaming, AMD is confident in the RX 9070 GRE being a 1440p-class gaming GPU. The card will be available from today, June 1st, through AMD's various add-in board (AIB) partners, including Sapphire, PowerColor, ASRock, XFX, GIGABYTE, Acer, and ASUS.

Today, AMD released the AMD Ryzen 9 9950X3D2 Dual Edition processor, the first processor that brings dual AMD 3D V-Cache technology to the desktop, unlocking a new level of performance for developers, creators and gamers.

Built for demanding developers, the AMD Ryzen 9 9950X3D2 Dual Edition processor combines high-performance "Zen 5" core technology with dual 2nd Gen AMD 3D V-Cache technology across all 16 cores, delivering 208 MB of total cache for expanded cache capacity and low latency. The result is exceptional responsiveness, increased throughput and flexibility to power next-generation development and creation workflows.

Sapphire introduced two new China-specific graphics cards, the Radeon RX 9070 GRE Pulse Pro, and the Radeon RX 9060 XT Pulse S. The two feature a price-performance ratio that's highly optimized for the Chinese market, banking on the success of China-specific products from previous generations. The RX 9070 GRE Pulse Pro features a board design that's similar to that of the RX 9070 series Pure brand from the company, but colored black overall. The card appears high-end when installed, with a meaty triple-slot cooling solution, and a board length of 32 cm. It uses a pair of 8-pin PCIe power inputs. Sapphire has given this card a Game clock of 2920 MHz boost, and 2340 MHz Game clock. Display outputs include two each of HDMI 2.1b and DisplayPort 2.1a.

Carved out from the 4 nm "Navi 48" silicon, the RX 9070 GRE has 48 RDNA 4 compute units, for 3,072 stream processors. It gets 12 GB of 20 Gbps GDDR6 memory across a 192-bit wide memory bus. The RX 9070 GRE is hence positioned between the global RX 9070 and RX 9060 XT 16 GB. Next up, is the Sapphire Radeon RX 9060 XT 8 GB Pulse S. This is a compacted version of the global RX 9060 XT 8 GB Pulse. While the global card has a 24 cm board length with 12.4 cm height, the China-specific Pulse S card is just 20 cm in length, with 12.2 cm height. Both cards are 2 slots thick.

TrendForce's latest research on the foundry industry reveals that continued investment in the AI arms race by North American CSPs and AI startups will keep demand for AI processors and supporting ICs strong in 2026. Global foundry revenue is projected to grow 24.8% YoY to approximately US$218.8 billion, with TSMC expected to post the largest increase of around 32% YoY.

Demand for advanced nodes will continue to be driven by AI GPUs from companies such as NVIDIA and AMD. Meanwhile, North American CSPs, including Google, AWS, and Meta, and AI startups such as OpenAI and Groq, are accelerating the development of their own AI chips. Many of these designs are expected to enter volume production and begin shipping in 2026, becoming key drivers for 5/4 nm and more advanced process technologies.

Samsung Foundry has struck gold as its utilization rate has jumped to an impressive 80% this quarter. This comes after many years of struggling to achieve a good utilization rate, while competitors like TSMC have consistently led the adoption of newer nodes and gained a massive customer base. However, the situation has now changed, and Samsung's foundries are now operating at about 80% of total capacity, consistently producing silicon, with the Pyeongtaek Campus P2 and P3 leading the charge. Previously, these lines were only achieving a 50% booking rate last year and even struggled with insufficient production volume in the second half of 2024. Samsung uses these sites to manufacture 4 nm, 5 nm, and 7 nm nodes, which are now considered "mature," as the leading edge shifts to sub-3 nm production.

Part of the foundry revival is attributed to the strong demand for its 6th-generation HBM, coming in the form of HBM4 with a custom base die manufactured on the 4 nm node. While competitors are making HBM4 base dies on older nodes, Samsung is using a 4 nm custom base die that provides higher design density for any logic that ASIC makers want to implement. This can include some data processing that will aid the main accelerator in AI workloads. This has translated into high demand for Samsung Foundry products from external customers, who are now keeping production at high capacity.

Samsung Electronics Co., Ltd., a global leader in advanced memory technology, today announced that it has begun mass production of its industry-leading HBM4 and has shipped commercial products to customers. This achievement marks a first in the industry, securing an early leadership position in the HBM4 market. By proactively leveraging its most advanced 6th-generation 10 nanometer (nm)-class DRAM process (1c), the company achieved stable yields and industry-leading performance from the outset of mass production—all accomplished seamlessly and without any additional redesigns.

"Instead of taking the conventional path of utilizing existing proven designs, Samsung took the leap and adopted the most advanced nodes like the 1c DRAM and 4 nm logic process for HBM4," said Sang Joon Hwang, Executive Vice President and Head of Memory Development at Samsung Electronics. "By leveraging our process competitiveness and design optimization, we are able to secure substantial performance headroom, enabling us to satisfy our customers' escalating demands for higher performance, when they need them."

Intel's 10 years of integrated graphics have yielded massive performance improvements, according to recent testing by Phoronix. The latest testing shows that moving from Intel Gen 9 integrated graphics in the "Kaby Lake" CPUs introduced in 2016 to the modern Intel Arc B390 with Xe3 cores in "Panther Lake," results in a 12x performance boost and a 8x performance-per-watt efficiency increase. This is remarkable progress for Intel's iGPU team, delivering steady performance improvements year-over-year, with a significant boost in recent years. Phoronix tested iGPUs of top-end Core models, including: Core i7 8550U "Kaby Lake," Core i7 8565U "Whiskey Lake," Core i7 1065G7 "Ice Lake," Core i7 1185G7 "Tiger Lake," Core i7 1280P "Alder Lake," Core Ultra 7 155H "Meteor Lake," Core Ultra 7 258V "Lunar Lake," and finally the Core Ultra X7 358H "Panther Lake" processor.

The oldest among these is the "Kaby Lake" generation, which utilized Intel UHD Graphics 620 on Gen 9 architecture, while the newest is Intel's most powerful creation to date—Arc B390 based on Xe3 cores. Comparing the 14 nm FinFET Intel node to the TSMC N3E node reveals a massive gap not only in performance but also in efficiency. In the geometric mean of all test results, Intel has achieved an 11.97x performance improvement from the 14 nm Gen 9 iGPU era to the modern 3 nm Xe3 iGPU era. This performance increase is accompanied by a significant efficiency gain, resulting from new nodes and more work done per watt, which Phoronix calculated to be 8x. While the "Lunar Lake" platform is the smaller power consumer with an average power draw of 13.82 W and a maximum of 36.97 W, "Panther Lake" uses a slightly higher average of 26.86 W and a maximum draw of 55.59 W for nearly twice the result.

MediaTek has announced Dimensity 9500s and Dimensity 8500. As the latest members of the Dimensity family, both products focus on delivering outstanding performance, efficiency, AI, imaging, gaming, and wireless connectivity, driving new momentum into the flagship and premium smartphone segments.

"As leaders in smartphone global share, we are committed to increasing our investment in advanced technologies and striving to make bleeding-edge products available to more people," said JC Hsu, corporate senior vice president at MediaTek and general manager of the Wireless Communications Business Unit. "This mission is evident in this pair of Dimensity chipsets, which are intended to provide more flagship and premium smartphone experiences while upholding our vision in bringing the best possible performance and power efficiency to more people."

Late last month, AMD's speculated Ryzen 9 9950X3D2 and Ryzen 7 9850X3D gaming CPUs reportedly moved closer to becoming a reality. A series of late 2025 leaks have pointed to an eventual introduction of expanded Ryzen 9000 series "Zen 5" desktop product range; possibly at this week's CES trade show. The Ryzen 7 9850X3D SKU has broken cover on numerous occasions, even emerging very briefly from an official source last November. Fresh sleuthing activities have focused on a French e-tailer: LDLC—as evidenced by VideoCardz receiving a tip-off earlier today. The LDLC webstore has inadvertently listed Team Red's not-yet-launched Ryzen 7 9850X3D CPU model, in retail and tray (OEM) forms. Both product pages bear the same release date: January 29, 2026.

Also, a very specific "3 PM" local launch time is mentioned. No pricing details are outlined (at the time of writing), but basic specifications seem to align with past leaks—again, we are looking at an 8-core 16-thread "Granite Ridge" processor, destined for the AM5 socket. Additionally, the two active pages outline base 4.7 GHz and turbo/boost 5.6 GHz clocks, (a total of) 104 MB of 3D V-Cache, a 4 nm node process, and a 120 W TDP rating. Mid-way through December, a Swiss shop presented a $553 price point (by mistake)—positioning the new chip about $70 over the related Ryzen 7 9800X3D SKU (at launch MSRP). Interestingly, the LDLC site does not list the more mysterious Ryzen 9 9950X3D2 SKU.

Update: A VideoCardz follow-up report claims/re-confirms that AMD's Ryzen 7 9850X3D processor will arrive at retail outlets on January 29 (9 am EST), based on information in a leaked sales embargo document. Apparently, no pre-sales are permitted—meaning that pre-orders will not be opened up when reviews start appearing online.

Early last week, AMD briefed members of the press about a new Ryzen AI 400 series coming to desktop in the near future. At the time, details and visual material were scarce—fundamentally, 4 nm "Gorgon Point" monolithic silicon seems to be freeing itself from mobile platform origins. As CES 2026 wrapped up, detective work continued online. Late last week, VideoCardz realized that Saša Marinković (a senior director of Global Consumer Marketing at Team Red) had captured an important moment during Dr. Lisa Su's on-stage presentation at Lenovo Tech World.

In the background, a projected slide showed off three important upcoming new-gen families: EPYC, Instinct (accelerator), and the aforementioned Ryzen AI PRO 400 APU design. The latter was rendered/depicted in desktop socketed format, on the familiar AM5 platform. This likely reaffirms previous reports that AMD has moved on from past-gen desktop APU nomenclature; e.g. Ryzen 8000G. Up until the start of this year, many industry observers predicted an introduction of Ryzen 9000G APU products, armed with XDNA 2 NPUs, at the important January trade event. Going further into 2026, Team Red is expected to announce various Ryzen AI 400 desktop SKUs, featuring Zen 5/Zen 5c core configurations and RDNA 3.5-based iGPUs.

AMD announced in its CES media briefing that its upcoming Socket AM5 desktop APUs that succeed the Ryzen 8000G series will be branded under the Ryzen AI 400 series, in line with its new Ryzen AI 400 series mobile processors that these share the underlying silicon with. While the company did not release specifics such as processor models, it dropped enough material to show that Ryzen AI 400 series desktop APUs will be based on the same 4 nm "Gorgon Point" monolithic silicon as the mobile Ryzen AI 400 series. These will be the world's first socketed desktop processors with an NPU that meets Microsoft Copilot+ hardware requirements. Until now, only mobile-on-desktop (MoD) platforms offered Copilot+, by using mobile processors in desktop form-factors such as mini PCs and AIOs.

The "Gorgon Point" silicon is physically identical to "Strix Point," with the same exact IP blocks, but AMD has refreshed its power management logic to carve out increased clock speeds across its three main logic components, the CPU, the iGPU, and the NPU. The CPU now boosts up to 5.20 GHz for its "Zen 5" cores, while the iGPU engine clock now goes up to 3.10 GHz. The NPU clock is increased, too, and now offers a throughput of 60 TOPS over the 55 TOPS of "Strix Point." AMD did not disclose the processor models of its Socket AM5 Ryzen AI 400 series chips, but these could be a handful of SKUs (2-3 in the consumer segment), with one maxed-out SKU that has all 12 CPU cores (4x Z5 + 8x Z5c), iGPU with all 16 CU, and 60 TOPS NPU; followed by another SKU that comes with a 10-core/20-thread CPU, 12 iGPU CU, and a 55 TOPS NPU; and a mid-range chip with 8-core/16-thread CPU, 8 or 12 iGPU compute units, and a 50 TOPS NPU. All three chips could come with a TDP of 65 W, with PPT nearing the 100 W-mark.

AMD at the 2026 International CES announced the new Ryzen AI 400 series "Gorgon Point" mobile processors powering the company's client processor lineup through 2026. These chips are based on the new 4 nm "Gorgon Point" silicon that is a refresh of the current "Strix Point" monolithic processor supporting higher clock speeds across its various compute components, and updates to its power management. The processor implements the "Zen 5" microarchitecture, and uses a dual-CCX CPU with four full-sized "Zen 5" cores sharing a 16 MB L3 cache, and eight compact "Zen 5c" cores sharing an 8 MB L3 cache. The "Zen 5" cores boost up to 5.20 GHz, while the iGPU goes up to 3.10 GHz engine clock. The chip features an iGPU based on the RDNA 3.5 graphics architecture with 16 compute units (CU). Both the CPU and iGPU feature improved boost residency over "Strix Point."

Besides the CPU and iGPU, the integrated NPU also gets a performance uplift, with increased NPU clock speeds enabling a peak throughput of 60 TOPS, up from 55 TOPS on Ryzen AI 300 series processors. AMD has also given the processor a feature-packed ROCm software stack, so client AI software can leverage this 60 TOPS NPU and the AI acceleration capabilities of the iGPU and CPU. Lastly, AMD has updated the integrated memory controllers, giving them native support for LPDDR5X 8533 MT/s memory speeds, an increase from the 8000 MT/s that "Strix Point" natively supports. Despite these improvements, "Gorgon Point" remains mostly similar to "Strix Point" at a physical level, and so AMD took the opportunity to refresh the way the various Ryzen AI 400 series processor models are segmented from this silicon, giving each SKU an improvement over its Ryzen AI 300 series predecessor. This could be anything from CPU clock speeds, to CPU core-count, to iGPU CU count, and NPU throughput.

Semiconductor industry insiders reckon that TSMC leadership has revised its production strategies for a Japan-based fabrication site. The Taiwanese foundry business owns a majority stake in Japan Advanced Semiconductor Manufacturing (JASM). This partnership lead to a "Fab 23 phase 1" plant coming online a year ago, in the Kumamoto Prefecture. This factory is tasked with producing past-gen-sized wafers; at best on a 12 nm process node. A neighboring "phase 2" foundry is still under construction, but fresh inside track info proposes that certain activities have been put on hold. Initially, the "Fab 23 phase 2" (also known as "JASM phase 2") was categorized as a 6 nm and 7 nm chip production specialist, with building work expected to end by 2027. Rumors from late 2023 indicated company bigwigs "mulling" over a jump up to an N4 process. This year's surging demand for AI-grade hardware has reportedly prompted another reassessment of JASM production outlooks.

Nikkei Asia alleges that TSMC is "considering using its second plant in Japan to make more advanced chips than originally planned." According to publication's unnamed sources, the still in-progress phase 2 site could take on the challenge of dealing in N4 and N5. Lately, demand for 6 nm and 7 nm products has diminished. Tom's Hardware has looked into the latest claims, their resultant report highlights a major pause of construction: "one interesting thing to note about TSMC's Fab 23 phase 2 is that while it entered the early phase of physical build-out in late October (according to Nikkei), photos taken at the site in November showed cranes, excavators, and piledrivers on site. However, images captured in early December reveal that nearly all heavy equipment has since been removed. Also, suppliers were notified that work would pause, although no reasons were provided." Additionally, Nikkei's insiders claim that new equipment orders are on hold—the two Japanese sites will not require any additional tools "throughout 2026."

Pleasing progress at TSMC's Arizona location has resulted in company leadership expediting a "push into advanced node deployment." Mid-October reports cited an increased domestic demand for 2 nm-class wafer products. Despite the foundry industry leader and NVIDIA's public celebration of debut "made in the USA" NVIDIA "Blackwell" wafers, TSMC's Phoenix-adjacent campus lacks in one key area: advanced packaging. Not long after the conclusion of festivities, computer hardware news outlets highlighted Fab 21-produced (4 nm) Blackwell products being sent overseas—specifically, back to Taiwan—for Chip on Wafer on Substrate (CoWoS) treatments.

Later on in October, TechPowerUp's AleksandarK covered the importance of advanced packaging on North American soil. His special editorial piece focuses on Intel Foundry's potential advantages in this area of expertise; thus poised to take a leading position within the region's semiconductor industry. Yesterday, Taiwan's Liberty Times outlined a major near-future change for one section's of TSMC Arizona's vast spread: "(leadership) plans to convert the land of the planned sixth phase fabrication plant (P6 fab) into an advanced packaging (AP) plant. If the construction goes smoothly, it is expected to be installed as early as the end of 2027 and enter the pre-production stage." Some of the claimed inside track timelines seems to roughly align with previous reports of TSMC and Amkor Technology's $7 billion forthcoming "advanced outsourced semiconductor packaging and testing" facility.

AMD's Radeon RX 9070 and Radeon RX 9070 XT graphics cards have finally reached their MSRPs of $549 and $599, respectively. According to US retailer Newegg listing, these GPUs are now trading at the price AMD artificially set at the launch eight months ago. AMD's AIB partners have used this MSRP model as a general guide, but priced the cards historically higher to preserve margins. Since no reference Made by AMD (MBA) cards were shipped to the masses, AMD's MSRP had little influence over the pricing decision made by AIB partners. Consumers couldn't get MBA cards at their MSRPs, so they had to opt for custom PCB designs from third parties like ASUS, Sapphire, ASRock, XFX, and others. Since all of these were custom designs, AIBs have priced it higher to account for custom engineering going into their GPUs.

Thankfully, gamers can now get both the Radeon RX 9070 and Radeon RX 9070 XT at AMD-set MSRP at US retailers like Newegg. Below, you can check out the images from Newegg for PowerColor Reaper Radeon RX 9070 trading at $549 and ASRock Challenger Radeon RX 9070 XT trading at $599. As a reminder, AMD launched both the Radeon RX 9070 XT and RX 9070 on March 6th, 2025. Both cards are built on the 4 nm process using Navi 48 chips and come with 16 GB of GDDR6 memory and PCIe 5.0 x16 connectivity. The RX 9070 XT uses the Navi 48 XTX variant and features 4096 SPs, 64 ray tracing acceleration cores, and 128 tensor cores. It can boost up to 2970 MHz, and has a maximum power draw of 304 W. The RX 9070, meanwhile, uses the Navi 48 XT variant with some shaders disabled, resulting in 3584 SPs, 56 ray tracing acceleration cores, and 112 tensor cores. It boosts up to 2520 MHz and draws up to 220 W.

Just three days ago, NVIDIA and TSMC celebrated the production of the first "Blackwell" GPU at TSMC's Fab 21 complex in Phoenix, Arizona. This marked a significant milestone for both companies, as it signifies the creation of the world's most powerful silicon on U.S. soil. However, the production phase is only part of the story, as the chip benefits not only from an advanced node but also from TSMC's advanced packaging systems. Specifically, the Blackwell family of GPUs utilizes TSMC's Chip on Wafer on Substrate (CoWoS) packaging system.

For CoWoS access, TSMC must send these chips back to the Taiwanese facilities overseas and house the raw die in a CoWoS-S configuration with silicon interposer. This establishes a supply chain dependency on Taiwanese facilities, which remain essential for completing the production of advanced silicon. As a result, the chip isn't entirely manufactured on American soil, indicating that some issues still need to be resolved. TSMC produces NVIDIA's Blackwell chips using a custom 4N 4 nm class node specifically designed for NVIDIA. This die is paired with eight stacks of HBM3E, all housed within a CoWoS-S package.

TSMC's strategy to keep advanced manufacturing primarily in Taiwan might be shifting, as indicated by recent comments from CEO C.C. Wei. During the Q3 earnings call, Wei stated, "We are preparing to upgrade our technologies faster... to more advanced process technologies in Arizona, given the strong AI-related demand from our customers." Previously, TSMC has emphasized that its latest nodes would be developed in Taiwan first, with Arizona following. Currently, TSMC produces N4 4 nm technology at its Arizona facilities and had planned to introduce the N3 node in 2028. However, this plan might change in favor of developing more advanced N2 or even A16 nodes in the coming years, as Taiwanese facilities advance to the A16 and A14 nodes first. The U.S. fabs will remain one node generation behind the Taiwanese fabs, rather than several generations as initially planned.

The push to accelerate advanced node deployment is largely driven by demand from U.S. customers. TSMC recently confirmed that its most advanced N2 node will begin volume production by the end of the year, with a rapid increase planned through 2026 in Taiwan. This marks the second 2 nm-class node to reach high-volume manufacturing, following Intel's 18A node. The competition from Intel's 18A and the upcoming 14A ramp may have led TSMC to reconsider its strategy for bringing advanced manufacturing to its U.S. facilities. While TSMC plans to add five more facilities at its Fab 21 site, it is yet to be confirmed which nodes will be developed there. With an accelerated timeline, it seems only a matter of time before we see the first Angstrom-era nodes produced on American soil.