kazuvikingIntel really loves their rectangle packaging.

wNotyarDI won't complain about that because it makes easier for everyone to design thermal solutions for them. But those dummies do look like a lot of wasted space.

GenericUsername2001It is interesting that the compute tiles will be on TSMC N2P, pretty much the same process Zen 6 cpu chiplets will be using. Will allow for some nice apples to apples comparisons on how good each company's actual designs are.

wNotyarDI won't complain about that because it makes easier for everyone to design thermal solutions for them. But those dummies do look like a lot of wasted space.

NhonhoWhen the main components of a processor (the cores, memory controller, iGPU, and PCIe controller) are placed on separate dies, the communication latency between them increases significantly. As a result, any performance gains from the individual components are diminished. This reduces the performance-per-watt of the entire chip, necessitating higher clock speeds to compensate for the high internal communication latencies—not to mention the need to include a large (and expensive) amount of cache memory to offset those same latencies.

Why don't they make CPUs as simple and efficient as this?

kondaminweird they are using tsmc for mobile chips, where 18a is supposed to be great at thermals

AntiX3DGlazerMost of the active silicon is actually 18A-P, only the graphics tile (Intel 3) and the compute tile (N2P) aren't.

GenericUsername2001It is interesting that the compute tiles will be on TSMC N2P, pretty much the same process Zen 6 cpu chiplets will be using. Will allow for some nice apples to apples comparisons on how good each company's actual designs are.

XeonsNOpteronsIt just does not make sense to use the likely much more performant 18A-P on the peripheral tile and not the compute tile when they look pretty much the same area.

kondaminyeah, the tiles that see the most action

GeddagodLet's not forget it also allows us a comparison with a bunch of ARM cores. Really exciting time for people who want to look at how x86 and arm match up on equal foundry footing for perf and area, if not power (different form factors).

That's the issue, 18A-P is not likely much more performant.

Kinda telling abt how Intel sees how competitive 18AP is.
Ik Intel has publicly said they think 18AP is in between N2P and N3 PPA but I imagine for them to be going external, again, 18AP would be falling much more on the N3 side of that spectrum. Especially for perf.

kondaminor they don't have the chips because yields aren't where they need to be to supply both server demand and mobile

kondaminor they don't have the chips because yields aren't where they need to be to supply both server demand and mobile

kazuvikingDidn't intel abandoned TSMC and moved NVL production inhouse on 18A after not enough wafer capacity and sky high prices?

Hyderzwonder these gonna get some big friggin cache lovin for the mobile variants :D

wNotyarDBut those dummies do look like a lot of wasted space.

NhonhoWhy don't they make CPUs as simple and efficient as this?

XeonsNOpteronsIt just does not make sense to use the likely much more performant 18A-P on the peripheral tile and not the compute tile when they look pretty much the same area.

thestryker6It absolutely does make sense if you take a step back and look at timelines. Intel undoubtedly made the decision to secure TSMC N2 capacity pretty early in the production life of 18A. It had variance issues into this year which means this was absolutely going on when that decision was made. There was also no guaranteed timeline on 18A-P being ready for full volume production. Given that the first high volume part which is supposed to come out using 18A-P is DMR it actually makes sense to run NVL tiles through that process node. The IO tiles do not need to meet the same strict requirements that a Compute or Graphics tile would, but they still get to test the node using CPU IP thanks to the LPE cores.