Tuesday, September 24th 2019
AMD Could Release Next Generation EPYC CPUs with Four-Way SMT
AMD has completed design phase of its "Zen 3" architecture and rumors are already appearing about its details. This time, Hardwareluxx has reported that AMD could bake a four-way simultaneous multithreading technology in its Zen 3 core to enable more performance and boost parallel processing power of its data center CPUs. Expected to arrive sometime in 2020, Zen 3 server CPUs, codenamed "MILAN", are expected to bring many architectural improvements and make use of TSMC's 7nm+ Extreme Ultra Violet lithography that brings as much as 20% increase in transistor density.
Perhaps the biggest change we could see is the addition of four-way SMT that should allow a CPU to have four virtual threads per core that will improve parallel processing power and enable data center users to run more virtual machines than ever before. Four-way SMT will theoretically boost performance by dividing micro-ops into four smaller groups so that each thread could execute part of the operation, thus making the execution time much shorter. This being only one application of four-way SMT, we can expect AMD to leverage this feature in a way that is most practical and brings the best performance possible.AMD isn't the first to implement this kind of solution to its processors. IBM has been making CPUs based on POWER ISA for years now that feature four or even eight-way SMT and they are one of the key reasons why POWER CPUs are so powerful. Nonetheless, we can hope to see more details about Zen 3 core design decisions as we approach 2020 and launch of Milan CPUs.
Source:
Hardwareluxx
Perhaps the biggest change we could see is the addition of four-way SMT that should allow a CPU to have four virtual threads per core that will improve parallel processing power and enable data center users to run more virtual machines than ever before. Four-way SMT will theoretically boost performance by dividing micro-ops into four smaller groups so that each thread could execute part of the operation, thus making the execution time much shorter. This being only one application of four-way SMT, we can expect AMD to leverage this feature in a way that is most practical and brings the best performance possible.AMD isn't the first to implement this kind of solution to its processors. IBM has been making CPUs based on POWER ISA for years now that feature four or even eight-way SMT and they are one of the key reasons why POWER CPUs are so powerful. Nonetheless, we can hope to see more details about Zen 3 core design decisions as we approach 2020 and launch of Milan CPUs.
159 Comments on AMD Could Release Next Generation EPYC CPUs with Four-Way SMT
1) Intel offered 4 threads per core in Xeon Phi.
2) 4-way SMT was also included in processors by IBM, Sun and MIPS.
So despite AMD being called "innovative" by some in this thread, they're actually pretty late with this feature.
Sorry to ruin the AMD hype party.
Moreover, there's not much gain from 4-way SMT in general tasks, so don't expect this to be magically twice as fast. This works best in highly optimized compute clusters.
www.theregister.co.uk/2018/06/18/microsoft_e2_edge_windows_10/
Does it mean its a good idea? No. So how about semantics of three layer deep "we could, but should we?" is left alone and we focus on what going to improve performance.
And Phi wasn't a failure because of its SMT implementation.
Nah brah. I never said Intel didn't have it, if I did, good job on proving they had it on a niche product that doesn't matter, I was discussing how it might affect the performance of the core. Intel has it, but it sucked, IBM has it, and it works. AMD is going to try it, and its probably better left in server space.
You replied to my comment about the difference in CISC and RISC designs with a statement that Phi ran Windows 10, poorly, I can make things that work good work poorly as well, but in the name of time and sanity I choose not to. But /end discussion..... thats awesome. Go you.... far away.
How much more does this duck need to quack?
Given the fact that I did not mention CISC or RISC in my response, it's pretty obvious I wasn't commenting on that portion of your post.
Phi is x86 compliant. People have successfully run OSes on it (even Windows).
Xeon Scalable is an evolution of Phi, so it shouldn't be hard for Intel to include 4-way SMT.
Aldain said this: I responded with information about Intel microprocessors which feature 4-way SMT.
Any commentary on the economic or technical success of products derived from this micro-architecture have no bearing on the fact that it exists.
Umm, I'll take the AMD SMT (any) desktop processor at 105w @ 3.8ghz instead lol.
Guess the 90% of CPUs throughout history that don't utilize the x86 ISA aren't CPUs in your book.
Must be hard being that myopic. What's your prescription? This isn't anywhere near as difficult as you're making this. Aldain said "Intel never made a CPU with 4-way SMT", I provided the proof that they have. I made no commentary on its success or viability as a commercial product.
Turds are turds, even if yer first with a turd?
IF your a gramma tart ,you should well know all sentences start with a capital, im not.