Tuesday, September 24th 2019

AMD Could Release Next Generation EPYC CPUs with Four-Way SMT

AMD has completed design phase of its "Zen 3" architecture and rumors are already appearing about its details. This time, Hardwareluxx has reported that AMD could bake a four-way simultaneous multithreading technology in its Zen 3 core to enable more performance and boost parallel processing power of its data center CPUs. Expected to arrive sometime in 2020, Zen 3 server CPUs, codenamed "MILAN", are expected to bring many architectural improvements and make use of TSMC's 7nm+ Extreme Ultra Violet lithography that brings as much as 20% increase in transistor density.

Perhaps the biggest change we could see is the addition of four-way SMT that should allow a CPU to have four virtual threads per core that will improve parallel processing power and enable data center users to run more virtual machines than ever before. Four-way SMT will theoretically boost performance by dividing micro-ops into four smaller groups so that each thread could execute part of the operation, thus making the execution time much shorter. This being only one application of four-way SMT, we can expect AMD to leverage this feature in a way that is most practical and brings the best performance possible.
AMD isn't the first to implement this kind of solution to its processors. IBM has been making CPUs based on POWER ISA for years now that feature four or even eight-way SMT and they are one of the key reasons why POWER CPUs are so powerful. Nonetheless, we can hope to see more details about Zen 3 core design decisions as we approach 2020 and launch of Milan CPUs. Source: Hardwareluxx
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159 Comments on AMD Could Release Next Generation EPYC CPUs with Four-Way SMT

#76
R0H1T
techguymaxc, post: 4121892, member: 190760"
This isn't anywhere near as difficult as you're making this. Aldain said "Intel never made a CPU with 4-way SMT", I provided the proof that they have. I made no commentary on its success or viability as a commercial product.
You're still twisting it any which way you like, technically it is not a CPU ~ it was always designed as a co-processor. Need I remind you of the difference between the two?
Posted on Reply
#77
cucker tarlson
theoneandonlymrk, post: 4121904, member: 82332"
if your going to be a gramma tart , get your shit right .
no,just doesn't make sense.
Posted on Reply
#78
techguymaxc
R0H1T, post: 4121906, member: 131092"
You're still twisting it any which way you like, technically it is not a CPU ~ it was always designed as a co processor. Need I remind you of the difference between the two?
I've already explained this. It runs the x86 ISA natively, and an Operating System can run on it. You're making a semantic argument, not a technical one.
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#79
ShrimpBrime
R0H1T, post: 4121906, member: 131092"
You're still twisting it any which way you like, technically it is not a CPU ~ it was always designed as a co processor. Need I remind you of the difference between the two?
ummm.... C- central P-processor U-unit // Co-processor.
THEY BOTH PROCESSORS!!!

lmao this thread rocks.
Posted on Reply
#80
notb
R0H1T, post: 4121889, member: 131092"
Yes & what was your point exactly, that 4 way SMT for AMD is not a major achievement ~ sure, I guess this why highlighting a product which was supposed to compete in HPC, but failed spectacularly is something noteworthy then?
No. As someone already said: we're just debunking the thesis that Intel hasn't offered 4-way SMT. That's it.
Any discussion about Phi being a success or not are pointless. SMT worked very well.

Also, given that Intel built their whole current Xeon lineup out of the Xeon Phi idea, I wouldn't really call it "a failure".

cucker tarlson, post: 4121897, member: 173472"
please say that again in English.
Please, don't go down that road.
@theoneandonlymrk can't use proper English and he gets very aroused when asked to work on this.
Posted on Reply
#81
cucker tarlson
notb, post: 4121911, member: 165619"
No. As someone already said: we're just debunking the thesis that Intel hasn't offered 4-way SMT. That's it.
Any discussion about Phi being a success or not are pointless. SMT worked very well.

Also, given that Intel built their whole current Xeon lineup out of the Xeon Phi idea, I wouldn't really call it "a failure".


Please, don't go down that road.
@theoneandonlymrk can't use proper English and he gets very aroused when asked to work on this.
I don't know what clouds,blades and special ones he's referring to.
epyc is not for gaming was my point,and I can't really respond to whatever point he made.
Posted on Reply
#82
ShrimpBrime
notb, post: 4121911, member: 165619"
Phi being a success or not are pointless. SMT worked very well.


@theoneandonlymrk can't use proper English and he gets very aroused when asked to work on this.
HT, it's Intel's Hyper Threading© Technology.....
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#85
thesmokingman
ShrimpBrime, post: 4121910, member: 185158"
ummm.... C- central P-processor U-unit // Co-processor.
THEY BOTH PROCESSORS!!!

lmao this thread rocks.
Hehe... but ugh doesn't the coprocesser actually need an actual CPU to work?
Posted on Reply
#86
notb
ShrimpBrime, post: 4121913, member: 185158"
HT, it's Intel's Hyper Threading© Technology.....
HT is a marketing name. SMT is the idea behind it.
And to not have heard about Xeon Phi is quite an achievement for a "PC enthusiast"
It seems you're really new in this...
Posted on Reply
#87
R0H1T
techguymaxc, post: 4121909, member: 190760"
I've already explained this. It runs the x86 ISA natively, and an Operating System can run on it. You're making a semantic argument, not a technical one.
Alright, how many systems around the world run just Xeon Phi even among those involved in HPC?
I'm not sure who's arguing semantics here, it is a processor as much as any GPU/FPGA/ASIC that can run an OS.
notb, post: 4121911, member: 165619"
Also, given that Intel built their whole current Xeon lineup out of the Xeon Phi idea, I wouldn't really call it "a failure".
Needs citation, unless you're saying the idea was AVX 512 :confused:
Posted on Reply
#89
notb
thesmokingman, post: 4121920, member: 91203"
Hehe... but ugh doesn't the coprocesser actually need an actual CPU to work?
No. A coprocessor is a function. It's a component that is used for compute tasks, but not for running the system. Much like GPU.

The chip that powered Xeon Phi accelerators was a x86 compliant processor. If you put it in a LGA3647 motherboard, it would have worked as a CPU.
Posted on Reply
#90
ShrimpBrime
notb, post: 4121921, member: 165619"
HT is a marketing name. SMT is the idea behind it.
And to not have heard about Xeon Phi is quite an achievement for a "PC enthusiast"
It seems you're really new in this...
Didn't take notice the (©) that was placed there? But for viewers that ARE new to this, perhaps some differentiation between the two chip makers would help people understand how this entire thread is derailed over something as simple as Simultaneous Multi-Threading on a new upcoming (perhaps not so revolutionary concept) kick-butt processors.

I must confess.... I know very little about anyting Intel has produced. I have overclocked a few, but has always been out of my price range. Especially server and workstation processors.

Would love to see 4 way SMT on AMD desktop processors though. At affordable pricing I must add....
Posted on Reply
#91
theoneandonlymrk
cucker tarlson, post: 4121919, member: 173472"
what does that have to do with what I said ? I never mentioned servers.Yes,servers do run on epyc processors.Thank you.
"epyc is not for gaming was my point"

And your points wrong, epyc is for the server yes but some of that resource is used to game on and for the next-gen console cloud platform for ps5 and xbox next , as well as their world-beating supercomputer will use an evolved epyc , or perhaps your links have told you different?.

Epyc and the Zen architecture are multi-purpose processors, designed to achieve many goals, not just one, and 2.5D packaging makes epyc or its next hybrid custom weird iteration nothing more than a validation away.

Thats why intel should be scared.

at this moment they would struggle to counter some things that AMD can do but have not yet done, epyc is a wonderful example of something intel cannot do.
Posted on Reply
#92
thesmokingman
Intel must have nightmares about Epyc, or is that Epyc nightmares?
Posted on Reply
#94
_Flare
4-way SMT is not what the article describes, it is not slicing an operation into 4 smaller ones, that is widely done by every x86-Decoder since its invention, not exactly 4 but more than 1 and increasing over the years, with a natural limit because an Op can only be sliced in a few µOps, not infinite ones.

Additionally that is advanced with the µOp mechanisms used widely since some years now, excessively since Sandy-Bridge with µOp-Caching.

What 4-way SMT is, is what IBM uses in their Power-Cores since some years now, it is like 1 Core executing 4 Threads, like a doubled Hyperthreading.
I think what IBM does in their ecosystem is not as efficient in the x86-ecosystem, additionally the actual SMT used with Zen2 is very efficient and most of the time better than what Intel offers.

They will advance both intel and AMD with the decoder and OoO-window and µOp-Caching and so on, like Intel recently teasered for IceLake.
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#95
CheapMeat
I believe IBM helped AMD with their SMT implementation.
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#96
Steevo
techguymaxc, post: 4121892, member: 190760"
If it can't run Crysis is it not a CPU in your opinion?

Guess the 90% of CPUs throughout history that don't utilize the x86 ISA aren't CPUs in your book.

Must be hard being that myopic. What's your prescription?



This isn't anywhere near as difficult as you're making this. Aldain said "Intel never made a CPU with 4-way SMT", I provided the proof that they have. I made no commentary on its success or viability as a commercial product.
Obvious joke is obvious. Can it run crysis has nothing to do with anything beyond the obvious question.

What performance level does it operate at that matters to the 99%?

If it's not easy, affordable, and powerful to use for the above average computer user it's not worth anything more than a side note*. Enter Itanium, Phi, and other vaporware.
Posted on Reply
#97
ShrimpBrime
Steevo, post: 4121959, member: 19251"
Obvious joke is obvious. Can it run crysis has nothing to do with anything beyond the obvious question.

What performance level does it operate at that matters to the 99%?

If it's not easy, affordable, and powerful to use for the above average computer user it's not worth anything more than a side note*. Enter Itanium, Phi, and other vaporware.
There it is right there.
Epic not for home pc use. No your grandmas dell wont have 256 threads any time soon.... Maybe....
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#98
dinmaster
Didn't Intel take some of their server cpu's or at least core counts etc and put them into consumer cpu's to be relevant? Certainly in the future this could be used as a way to keep Intel at bay or similar to what Intel did to keep relevant until the next micro architecture arrives..
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#99
springs113
theoneandonlymrk, post: 4121680, member: 82332"
Doesn't anyone watch Moore's laws deads videos on here, his leak gave him smt4 leaked weeks ago?
actually he mentioned it months ago
Posted on Reply
#100
Camm
I hope it comes with the ability to enable disable modify smt levels per core on the fly, as this could really shine if so.
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