Wednesday, May 6th 2026

AMD to Expand EPYC Lineup With Specialized CPUs for AI, HPC, and Cloud

May 6th, 2026 10:19 Discuss (31 Comments)

AMD's CPU offerings will soon expand into more categories, specializing in different tasks and use cases. During the latest Q1 earnings call, AMD CEO Dr. Lisa Su confirmed that customers are increasingly interested in specialized EPYC solutions and that future CPU generations will cater to different customer needs. This means that agentic AI will receive a dedicated EPYC CPU SKU, HPC workloads will have their own EPYC CPU SKU, AI training and inference will get a separate EPYC SKU, and cloud workloads will have a distinct SKU. This expansion of task-specialized CPU designs will go beyond the "Venice" CPU platform, which is expected to be released this year. At CES 2026, AMD confirmed that EPYC "Venice" will be a highly dense CPU package with up to 256 cores and 512 threads of "Zen 6c" cores, while the regular "Zen 6" configuration will have a maximum of 96 cores and 192 threads.

With this generation of EPYC CPUs based on the "Zen 6" core IP, AMD will promote "Venice" CPUs broadly, while the "Venice" CPU generation will be complemented by the "Verano" CPUs. These appear to use the same "Zen 6" microarchitecture but have optimizations specifically designed for AI infrastructure. Contrary to previous assumptions that "Verano" would be a "Zen 7" IP, it is now confirmed to be part of the 6th-generation EPYC CPU family. This indicates that AMD is starting its CPU customization for different workloads as early as this year. As the server CPU market is projected to reach $120 billion by the end of this decade, less than 3.5 years away in 2030, it makes sense to have different CPU SKUs for each task and capture a significant portion of that revenue. Server CPUs are also expected to grow at a 35% compound annual growth rate, which is impressive for a relatively mature market.

Finally, AMD is not the first to pursue this strategy. Intel has been customizing CPUs for hyperscalers since the early Xeon Scalable days, modifying power and core configurations in Xeon CPUs. With demand now being so varied, even a universal unit like a CPU can't meet all needs as a one-size-fits-all solution. Hence, AMD is also joining this trend, developing more solutions to power AI, HPC, cloud, and agentic AI era compute nodes worldwide.

Source: via Tom's Hardware

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31 Comments on AMD to Expand EPYC Lineup With Specialized CPUs for AI, HPC, and Cloud

twin_savage

Maybe AMD will finally sell us HBM CPUs?

LastDudeALive

This is an interesting choice, given how AMD's recent resurgence is heavily driven by the chiplet design and the economies of scale that provides. It's allowed them to undercut Intel on cost per core. Development is simple because they're only working on 1 architecture at a time, and it makes their supply chain easier to manage because CCDs are modular can go into whatever product is in demand at the time.

AleksandarK

News Editor

twin_savageMaybe AMD will finally sell us HBM CPUs?

www.phoronix.com/review/azure-hbv5-amd-epyc-9v64h

Patriot

AleksandarKwww.phoronix.com/review/azure-hbv5-amd-epyc-9v64h

Sell US, not micro$haft.

The closest consumers have gotten is kaby lake G, and that was for the amd gpu.

I think a lot of people got excited when AMD made the mi300A and had a giant apu with HBM, and microsoft got the MI300C whichwas renamed the Epyc 9V64H being on the Instinct packaging socket but only cpu cores, but there hasn't been a trickle down of the tech for us... power has consolidated to the cloud vendors.

Wirko

twin_savageMaybe AMD will finally sell us HBM CPUs?

Only Intel has a few of those, even you can buy them.

twin_savage

WirkoOnly Intel has a few of those, even you can buy them.

I was lucky enough to get some of these when they were on firesale.

Tek-Check

AleksandarKwhile the regular "Zen 6" configuration will have a maximum of 192 cores and 384 threads.

No. Regular Zen6 CCD has 12 big cores and new IOD on EPYC supports 8 attachment sites. So, regular EPYCs will top out at 96 cores.
Zen6c EPYC comes with 256 cores because Zen6c CCD features 32 cores. 32 c cores x 8 attachment sites =256 c cores.

AleksandarK"Verona" CPU generation will be complemented by the "Verano" CPUs.

Verona generation? Such thing does not exist. Are you able to confirm this code name? There is only Zen6 EPYC Venice with regular DDR5 and Zen6 EPYC Verano SKUs for LPDDR5X deployments in AI data centers, as confirmed by AMD. Please update as necessary.
www.amd.com/en/blogs/2026/a-look-ahead--extending-server-energy-efficiency-with-lpddr5x-me.html

Patriotthere hasn't been a trickle down of the tech for us...

HBM is not coming to consumer markets. Forget about it.

BoxCutter

I honestly don't get why people want HBM so bad, it's such a bad consumer deal, if there is something wrong with one chip the whole package is gimped, it's awful. It only really makes sense if you're super concerned about the battery life.

twin_savage

BoxCutterI honestly don't get why people want HBM so bad

So we can get our anemic memory bandwidth numbers up to match CPU performance increases. The phenomenon is called the processor "memory wall", where CPU performance has steadily been increasing at ~25% annual for the past several decades while memory performance increases at less than 10% annually.
The performance gap has grown very wide and we need something drastic to get back to "balance".

BoxCutterIt only really makes sense if you're super concerned about the battery life.

The way HBM has been developed wasn't really focused on being more power efficient than something like LPDDR, but HBM's performance scales much higher than LPDDR.

#10

LastDudeALive

twin_savageSo we can get our anemic memory bandwidth numbers up to match CPU performance increases. The phenomenon is called the processor "memory wall", where CPU performance has steadily been increasing at ~25% annual for the past several decades while memory performance increases at less than 10% annually.
The performance gap has grown very wide and we need something drastic to get back to "balance".

The way HBM has been developed wasn't really focused on being more power efficient than something like LPDDR, but HBM's performance scales much higher than LPDDR.

The problem is that more bandwidth (whether through more channels, faster RAM, HBM, etc) is expensive, and consumers have shown they generally prefer lower cost over increased performance. Additionally, enthusiasts who want more bandwidth also (generally) want the ability to change and upgrade their RAM, which means fast soldered RAM and HBM are out of the question. So desktops have stayed with the standard DIMM format, giving ordinary consumers the option of cheap but (relatively) slow RAM and enthusiasts fast but expensive premium kits.

What you should be watching is the new LPCAMM2 modules, which offer the high bandwidth of LPDDRX with the modularity of DIMMs. We will likely see some LGA-1954 mobos with LPCAMM2 instead of DIMM slots, like we saw DDR4 and DDR5 variants of LGA1700 mobos.

#11

twin_savage

LastDudeALiveThe problem is that more bandwidth (whether through more channels, faster RAM, HBM, etc) is expensive, and consumers have shown they generally prefer lower cost over increased performance.

It makes sense to keep the cost-conscious general consumer that aren't very demanding on traditional, cheap DDR/LPDDR, but enthusiasts and prosumers will want more.

LastDudeALiveAdditionally, enthusiasts who want more bandwidth also (generally) want the ability to change and upgrade their RAM, which means fast soldered RAM and HBM are out of the question. So desktops have stayed with the standard DIMM format, giving ordinary consumers the option of cheap but (relatively) slow RAM and enthusiasts fast but expensive premium kits.

There is a tipping point where the performance advantages outweigh the modularity benefits of DIMMs/CAMMs; where that line is is different for everyone, but If I could get double the performance out of a non-modular HBM/soldered design than a socketed memory design, I'd draw the line there personally.

LastDudeALiveWhat you should be watching is the new LPCAMM2 modules, which offer the high bandwidth of LPDDRX with the modularity of DIMMs. We will likely see some LGA-1954 mobos with LPCAMM2 instead of DIMM slots, like we saw DDR4 and DDR5 variants of LGA1700 mobos.

The problem with LPCAMM2 is motherboards are only ever going to have 1 of them on the PCB, which doesn't allow for wide memory interfaces. MRDIMMs have more potential here because 8, 12, 16 of them can all be connected to the CPU.

#12

atomsymbol

twin_savageSo we can get our anemic memory bandwidth numbers up to match CPU performance increases. The phenomenon is called the processor "memory wall", where CPU performance has steadily been increasing at ~25% annual for the past several decades while memory performance increases at less than 10% annually.
The performance gap has grown very wide and we need something drastic to get back to "balance".

Consider the following argument:

The memory latency and bandwidth gap exists in home PCs since year 1989 when Intel introduced the i486 CPU with on-chip L1D+L1I caches. The traditional way of solving the gap in PCs (which are modular designs) was to increase cache capacity - NOT to increase number of wires between the CPU and the DRAM modules. First, it was just L1 cache, then L2 cache was added, and then L3 cache.

Triple-channel or quad-channel memory in all CPUs would increase the cost of all motherboards and the cost of all CPUs - but the problem is that consumers are NOT willing to pay the extra costs because they can simply wait 2-3 years and buy a faster CPU with an improved cache hierarchy. This buying strategy is fairly effective: there is little performance gap between the cheaper new machine and [previous-generation costlier CPU with costlier triple/quad-channel memory].

Upcoming Zen 6 chiplet will have 48 MiB of L3 cache - this erases the advantage of having a a hypothetical Zen 5 CPU (32 MiB L3 cache per chiplet) with a triple-channel DDR5 memory interface. 24-core Zen 6 CPU will have 96 MiB of L3 cache where - due to a new lower-latency interconnect between the two Zen 6 chiplets - the other half of L3 cache (48 MiB) will have lower latency than the other half of L3 cache (32 MiB) in a 16-core Zen 5 CPU.

twin_savageThe way HBM has been developed wasn't really focused on being more power efficient than something like LPDDR, but HBM's performance scales much higher than LPDDR.

Lower power consumption was a design goal (key advantage) of HBM. It has much lower power consumption per gigabyte transferred than module-based DRAM, which is important for data centers.

#13

Tek-Check

twin_savageThe performance gap has grown very wide and we need something drastic to get back to "balance".

Buy Xeon or Threadripper. More memory bandwidth cost money, especially now. HBM is too precious in data centres and companies are far more willing to pay for it than consumers. Also, you can buy Xeon with HBM. Be prepared to pay for it.

twin_savageenthusiasts and prosumers will want more

Buy Xeon or Threadripper. Not sure what this faff is about. You can literally buy 4-channel or 8-channel PC right now.

#14

twin_savage

atomsymbolConsider the following argument:

The memory latency and bandwidth gap exists in home PCs since year 1989 when Intel introduced the i486 CPU with on-chip L1D+L1I caches. The traditional way of solving the gap in PCs (which are modular designs) was to increase cache capacity - NOT to increase number of wires between the CPU and the DRAM modules. First, it was just L1 cache, then L2 cache was added, and then L3 cache.

The problem with this method is that the larger you make you L# cache, the slower and less useful it becomes. Plus only certain applications that don't have much unique data going through them benefit from this, once you're hitting main memory for almost all of your data the cache does little.
Cross domain cache coherency is also a large problem, for example AMD's consumer processors access inter-CCD cache about as fast as they would access DDR5 memory; beefing up the IOD and fixing the infinity fabric performance would do wonders for the architecture over trying to increase cache size.

atomsymbolLower power consumption was a design goal (key advantage) of HBM. It has much lower power consumption per gigabyte transferred than module-based DRAM, which is important for data centers.

This is true, but the floor for your minimum amount of memory width is "16" or "32" memory channels on a single stack of HBM which is going to put your power usage over pretty much any implementation of LPDDR5.

#15

Tek-Check

LastDudeALiveWhat you should be watching is the new LPCAMM2 modules, which offer the high bandwidth of LPDDRX with the modularity of DIMMs. We will likely see some LGA-1954 mobos with LPCAMM2 instead of DIMM slots, like we saw DDR4 and DDR5 variants of LGA1700 mobos.

Wider adoption of CAMM2 and LPCAMM2 have been literally killed by current RAMageddon. Nobody is going to invest in shifting a serious part of consumer RAM ecosystem in these conditions. A few enthusiast solutions will exist, like Framework laptop and an odd desktop board, but that's it. DDR6 will be available on AM6 and post-1954, which means by ~2030, so by the time a few CAMM2 solutions on DDR5 standard are available, its physical layer will not be compatible with DDR6.

twin_savageThe problem with LPCAMM2 is motherboards are only ever going to have 1 of them on the PCB, which doesn't allow for wide memory interfaces. MRDIMMs have more potential here because 8, 12, 16 of them can all be connected to the CPU.

Desktop motherboards do not need more than two channels.
MRDIMMs will NOT be deployed in desktop, as those are not designed for desktop.

atomsymbolTriple-channel or quad-channel memory in all CPUs would increase the cost of all motherboards and the cost of all CPUs - but the problem is that consumers are NOT willing to pay the extra costs because they can simply wait 2-3 years and buy a faster CPU with an improved cache hierarchy. This buying strategy is fairly effective: there is little performance gap between the cheaper new machine and [previous-generation costlier CPU with costlier triple/quad-channel memory].

This.
The other dude can simply buy Xeon or Threadripper if they need more bandwidth.
I mean, how hard could it possibly be to understand the memory segmentation in products...

#16

twin_savage

Tek-CheckAlso, you can buy Xeon with HBM. Be prepared to pay for it.

These were selling for about the price of AMD's newest consumer AM5 processor not that long ago.

Tek-CheckBuy Xeon or Threadripper. Not sure what this faff is about. You can literally buy 4-channel or 8-channel PC right now.

Assuming we're talking about the currently available Xeon-W and Threadripper 7000/9000, they simply don't have that much memory bandwidth; even a 5090 is almost an order of magnitude more memory bandwidth, it's just I can't fit a problem of useful size into it's tiny amount of memory.

#17

Tek-Check

twin_savageThe problem with this method is that the larger you make you L# cache, the slower and less useful it becomes. Plus only certain applications that don't have much unique data going through them benefit from this, once you're hitting main memory for almost all of your data the cache does little.

As I said, you are looking for Xeon or Threadripper. Pay for it.

twin_savageCross domain cache coherency is also a large problem, for example AMD's consumer processors access inter-CCD cache about as fast as they would access DDR5 memory; beefing up the IOD and fixing the infinity fabric performance would do wonders for the architecture over trying to increase cache size.

Strix Halo has solved that, with new Infinity Fabric called 'sea of wires'. This will be deployed in all Zen6 CPUs.

twin_savageThese were selling for about the price of AMD's newest consumer AM5 processor not that long ago.

You need more memory channels? Pay for it.

twin_savageAssuming we're talking about the currently available Xeon-W and Threadripper 7000/9000, they simply don't have that much memory bandwidth; even a 5090 is almost an order of magnitude more memory bandwidth, it's just I can't fit a problem of useful size into it's tiny amount of memory.

You need to decide what it is that you need, more RAM bandwidth or more VRAM bandwidth, or both.
There are products that provide both.

#18

LastDudeALive

Tek-CheckWider adoption of CAMM2 and LPCAMM2 have been literally killed by current RAMageddon. Nobody is going to invest in shifting a serious part of consumer RAM ecosystem in these conditions. A few enthusiast solutions will exist, like Framework laptop and an odd desktop board, but that's it. DDR6 will be available on AM6 and post-1954, which means by ~2030, so by the time a few CAMM2 solutions on DDR5 standard are available, its physical layer will not be compatible with DDR6.

It could be the opposite. Since prices are already extremely high, the additional cost of CAMM2 will be significantly less in comparison. E.g. let's say a regular DIMM mobo is $200 and 32GB of DIMM RAM is $150, for a total of $350. If CAMM2 adds $100 of extra cost onto each of those, many people, even enthusiasts, wouldn't be willing to pay for it. But if 32GB of DIMM RAM is $500, then the total cost is $700 vs $900. That's a much smaller (proportional) gap. Enthusiasts are more likely to think "well, I'm already paying outrageous prices for RAM no matter what I get. Might as well pay a bit extra for more versatile form factor."

#19

atomsymbol

twin_savageThe problem with this method is that the larger you make you L# cache, the slower and less useful it becomes.

There is a major distinction between DDR5 and L3 cache: L3 cache has much higher bandwidth and the bandwidth scales with the number of CPU cores in a chiplet. Zen 5 L3 cache bandwidth (1 chiplet) is approximately 1 TiB/s (theoretical maximum appears to be 32B*8*5GHz=1280 GiB/s). Zen 6's max theoretical L3 cache bandwidth (1 chiplet, 12 cores) could be 32B*12*5.5GHz=2112 GiB/s - a significant improvement over Zen 5.

twin_savagePlus only certain applications that don't have much unique data going through them benefit from this, once you're hitting main memory for almost all of your data the cache does little.

A larger cache still does little? I think a larger cache does more than a smaller cache. It is why L2 and L3 cache have been increasing in size over time. ---- Increasing L1 cache size is impossible if frequency is also increasing - which is why Zen 5 has, approximately, the same L1 cache size as Pentium MMX (year 1996).

twin_savageCross domain cache coherency is also a large problem, for example AMD's consumer processors access inter-CCD cache about as fast as they would access DDR5 memory; beefing up the IOD and fixing the infinity fabric performance would do wonders for the architecture over trying to increase cache size.

Lowering inter-CCD latency is exactly what Zen 6 will do (better said: what it is rumored to do (because it hasn't been officially confirmed by AMD yet)).

#20

twin_savage

Tek-CheckAs I said, you are looking for Xeon or Threadripper. Pay for it.

Unfortunately as Patriot already stated, you can't buy them (9V64H) unless your name is Microsoft. That's why the article's headline had me hopeful, that AMD would start selling it's specialized/custom SKUs.

Tek-CheckStrix Halo has solved that, with new Infinity Fabric called 'sea of wires'. This will be deployed in all Zen6 CPUs.

They absolute did not, cross CCX latencies are up ~30% on Strix halo over normal Zen 5 as per Chipsandcheese. The high frequency SERDES design of the socketed Zen 5 CPUs is superior here; perhaps the problem is a first gen teething issue, but so far it doesn't look good compared to competing advanced packaging techniques that don't use an organic substrate.

Tek-CheckYou need to decide what it is that you need, more RAM bandwidth or more VRAM bandwidth, or both.
There are products that provide both.

Either would be great, if I can fit problems into GPU memory then I will code for a GPU, if not I must use CPU.

#21

Tek-Check

LastDudeALiveIt could be the opposite. Since prices are already extremely high, the additional cost of CAMM2 will be significantly less in comparison. E.g. let's say a regular DIMM mobo is $200 and 32GB of DIMM RAM is $150, for a total of $350. If CAMM2 adds $100 of extra cost onto each of those, many people, even enthusiasts, wouldn't be willing to pay for it. But if 32GB of DIMM RAM is $500, then the total cost is $700 vs $900. That's a much smaller (proportional) gap. Enthusiasts are more likely to think "well, I'm already paying outrageous prices for RAM no matter what I get. Might as well pay a bit extra for more versatile form factor."

Hahaha! Errr... no. It's not about buyers, it's about costs for mobo vendors. Global motherboard sales have taken a serious hit since RAM prices went up. The last thing in the world they would do is massively overhaul their main designs to serve CAMM2 modules. As I said, there will be a few, and that it. Forget about everything else.

#22

twin_savage

atomsymbolA larger cache still does little? I think a larger cache does more than a smaller cache. It is why L2 and L3 cache have been increasing in size over time. ---- Increasing L1 cache size is impossible if frequency is also increasing - which is why Zen 5 has, approximately, the same L1 cache size as Pentium MMX (year 1996).

Correct, if your L3 cache miss rate is high because most of your data is in main memory due to the size disparity between CPU cache and main memory (and CPU is processing data faster than prefetch can take it from slow main memory); perhaps I didn't explain that very good initially.
SRAM is basically done scaling with lithography improvements, so a larger cache needs to be spread out and propagation times become higher and thus the cache less performant; there is somewhat of an exception with 3D structures to this paradigm though.

atomsymbolLowering inter-CCD latency is exactly what Zen 6 will do (better said: what it is rumored to do (because it hasn't been officially confirmed by AMD yet)).

If this pans out it will be a big improvement, it looks similar to what Intel has been doing in their processors. TSMC's InFO-oS turned out to be kind of a dud for high performance.

#23

Tek-Check

twin_savageUnfortunately as Patriot already stated, you can't buy them (9V64H) unless your name is Microsoft. That's why the article's headline had me hopeful, that AMD would start selling it's specialized/custom SKUs.

Xeon Max, with HBM
www.intel.com/content/www/us/en/products/sku/232592/intel-xeon-cpu-max-9480-processor-112-5m-cache-1-90-ghz/specifications.html
www.techpowerup.com/cpu-specs/xeon-max-9480.c3084

twin_savageThey absolute did not, cross CCX latencies are up ~30% on Strix halo over normal Zen 5 as per Chipsandcheese. The high frequency SERDES design of the socketed Zen 5 CPUs is superior here; perhaps the problem is a first gen teething issue, but so far it doesn't look good compared to competing advanced packaging techniques that don't use an organic substrate.

Did you read the whole article by George and how testing was interpreted? Strix Halo was designed to make compromises due to large iGPU and shared memory. It behaves more like GPU with iCPU than the other way around. It does have more latency, but that's due to balancing act on this specific SKU. New Infinity Fabric layout is not a magic wand, but it will also be twice as faster on Zen6. Plus, Strix Halo is a different kind of product than classic desktop CPU, and therefore it's tuned differently.
chipsandcheese.com/p/strix-halos-memory-subsystem-tackling

twin_savageEither would be great, if I can fit problems into GPU memory then I will code for a GPU, if not I must use CPU.

Exactly. You will need to compromise between memory capacity and bandwidth.

#24

twin_savage

Tek-CheckXeon Max, with HBM

This is what I currently run, but it's getting kind of old and per-core performance isn't the greatest.

Tek-CheckDid you read the whole article by George and how testing was interpreted? Strix Halo was designed to make compromises due to large iGPU and shared memory. It behaves more like GPU with iCPU than the other way around. It does have more latency, but that's due to balancing act on this specific SKU. New Infinity Fabric layout is not a magic wand, but it will also be twice as faster on Zen6. Plus, Strix Halo is a different kind of product than classic desktop CPU, and therefore it's tuned differently.

It's likely there is alot going on under the hood as an APU, but previous socketed AMD APUs didn't experience this kind of regression. Perhaps it's still apples or oranges since Strix Halo is so much different than previous APUs though.

Tek-CheckExactly. You will need to compromise between memory capacity and bandwidth.

I want AMD to give me both. I'd be happy with as little as 256GB of RAM or VRAM.

#25

atomsymbol

twin_savageI want AMD to give me both. I'd be happy with as little as 256GB of RAM or VRAM.

I would like to argue that certain 'numbers' that historically have been important for computers have stopped increasing:

4K display resolution (27-32" monitor) is basically "the end of the road" for gaming - you do not need (or: shall not need) a higher resolution. What we need is improved color accuracy, not a higher resolution. VRAM in gaming PCs hasn't peaked yet, but when it reaches its peak I suppose it will be significantly less than 256 GB.
For users that use their notebooks mainly for web browsing, movies, email and office work: there is no need for more than 32 GB of RAM. Such users will _never_ be demanding 256GB of RAM.

Users (businesses) who need 256GB of RAM or VRAM in year 2026 are mainly those who care about security: for example they don't want to run large language models on remote cloud computers because somebody might steal their data, leak their data, or use their data without their consent.

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AMD to Expand EPYC Lineup With Specialized CPUs for AI, HPC, and Cloud

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