Monday, May 25th 2026

AMD "Zen 7" IP to Use TSMC A14 Node and More Advanced Packaging

by
AleksandarK
 Discuss (100 Comments)
AMD is gradually preparing to launch its next-generation "Zen 6" series of processors under the new EPYC "Venice" server CPU family. Meanwhile, development of the "Zen 7" architecture has been ongoing for quite some time, and it seems we are finally learning which manufacturing node AMD will use for this CPU generation. According to Taiwanese media outlet Commercial Times, AMD is reportedly considering TSMC's A14 node, officially utilizing the first angstrom-era node for its products. As readers may recall, AMD recently began high-volume production of its EPYC "Venice" on the 2 nm node, but with the upcoming "Zen 6" architecture. We have covered the advancements that "Zen 6" brings over the current "Zen 5," but the next-generation "Zen 7" is expected to elevate performance to a whole new level, especially with the power and performance enhancements of the new TSMC A14 node.

For "Zen 7" CCD IP codenamed "Grimlock," AMD plans to make its CPU architecture more AI-relevant, allowing future processing workloads to better leverage the processing power of 16 CPU cores per CCD. Among the key features are AVX10 and ACE. AVX10 unifies AVX-512 and AVX2 features to improve performance and compatibility across vector math-heavy workloads. ACE, or Advanced Matrix Extensions for Matrix Manipulation, is an industry-standard matrix math instruction set that could be relevant to a wide range of devices, from smartphones to servers. Other ISA additions with "Zen 7" include FRED (Flexible Return and Event Delivery), which replaces the current device interrupt model to reduce system-level latency. "Zen 7" also implements ChkTag x86 Memory Tagging to counteract various memory-level data vulnerabilities caused by buffer overflows and use-after-free errors.
Finally, AMD is reportedly exploring various packaging technologies, including next-generation 3D V-Cache technology. The company is said to be evaluating Powertech's FOPLP (Fan-Out Panel-Level Packaging) solution. Powertech, a silicon packaging vendor based in Taiwan, is recognized as one of the leading OSAT companies. As AMD explores different supply chain providers, Powertech has reportedly emerged as a potential option. The company currently offers various FOPLP technologies, so we are eager to see what AMD might choose for its "Zen 7" designs as it seeks to shift away from TSMC's dominance in silicon packaging.
Source: Commercial Times Taiwan

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100 Comments on AMD "Zen 7" IP to Use TSMC A14 Node and More Advanced Packaging

#1
Chaitanya
Given Zen6 is yet to launch, expecting Zen 7 to be atleast 2.5 years out in future.
Posted on Reply
#2
ncrs
FRED, in particular, was a noteworthy feature that Intel was working on for its x86S lightweight ISA standard.
It was not exclusive to x86S and is available in Panther Lake, usable at least under Linux and was benchmarked by Phoronix.
Posted on Reply
#3
AleksandarK
News Editor
ncrsIt was not exclusive to x86S and is available in Panther Lake, usable at least under Linux and was benchmarked by Phoronix.
Whaaat? Didn’t know that! Thanks
Posted on Reply
#4
_roman_
Does amd really want to drop their advantage with avx512? that makes any intel processor as of now a better deal.
Posted on Reply
#5
Tek-Check
AleksandarKFor "Zen 7" CCD IP codenamed "Grimlock," AMD plans to make its CPU architecture more AI-relevant, allowing future processing workloads to better leverage the processing power of 16 CPU cores per CCD.
How does the source know Zen7 codename and core count? It would be prudent to acknowledge the original source of this information, which is Tom from Moore's Law Is Dead. He was the first person globally to leak this information. His video on Zen7 leak was even taken down by YT, but it's back.

This is the original leak that you want to acknowledge, so that no one is in doubt.
_roman_Does amd really want to drop their advantage with avx512? that makes any intel processor as of now a better deal.
What are you talking about? They work together with Intel to advance several instruction sets on x86.
Posted on Reply
#6
ncrs
_roman_Does amd really want to drop their advantage with avx512? that makes any intel processor as of now a better deal.
AVX10 is backward-compatible with AVX-512 so they aren't dropping it.
Posted on Reply
#7
RejZoR
Is there any info on which will support AM5 and which will transition to socket AM6 ? I'm guessing Zen 6 at least will still run on AM5.
Posted on Reply
#8
jesdals
Well bring it on - looking forward to some positive PC news
Posted on Reply
#9
JustBenching
Zen 7 with 16 cores per CCD? That's nice, finally they are awake.
Posted on Reply
#10
jesdals
JustBenchingZen 7 with 16 cores per CCD? That's nice, finally they are awake.
Well if it ends up on AM5 it would also make AM5 a remarkable platform
Posted on Reply
#11
Wirko
jesdalsWell bring it on - looking forward to some positive PC news
Positive? With so much AI, the Spruce Pine Mine will inevitably run out of silica, and/or some other single-points-of-failure in the supply chain (which is a tree, not a chain) will fail.
jesdalsWell if it ends up on AM5 it would also make AM5 a remarkable platform
People will be trying to throw even more workstation work at this consumer platform. Expect more whining about poor I/O and memory bandwidth.
_roman_that makes any intel processor as of now a better deal.
As of now? Even if AMD were really going to abandon AVX512, do you think they will backport the lack of it to every CPU at retail stores waiting to be sold?
Posted on Reply
#13
jesdals
glen-the-greyToo early to say for Zen 7 but Zen 6 is confirmed by a few manufacturers to be on AM5:
Well if DDR6 is going to start at a even higher price point than DDR5 is at now - they might as well give Am5 another CPU
Posted on Reply
#14
The Von Matrices
jesdalsWell if DDR6 is going to start at a even higher price point than DDR5 is at now - they might as well give Am5 another CPU
New memory technologies are always more expensive at launch than what they are replacing. Sometimes that encourages manufacturers to release new platforms that support two memory standards, but I wouldn't count on a new chip with a new IMC that supports a new type of memory but also is backwards compatible with an old socket. That has only happened exactly once, with Phenom II. Every other time, the new chip required a new socket and new motherboard even if you could use the old memory in it.
Posted on Reply
#15
jesdals
The Von MatricesNew memory technologies are always more expensive at launch than what they are replacing. Sometimes that encourages manufacturers to release new platforms that support two memory standards, but I wouldn't count on a new chip with a new IMC that supports a new type of memory but also is backwards compatible with an old socket. That has only happened exactly once, with Phenom II. Every other time, the new chip required a new socket and new motherboard even if you could use the old memory in it.
Well this time around DDR6 would proberly cost 2 kidneys and an eye...
Posted on Reply
#16
user556
16 cores per CCD will be needing faster DRAM. Zen7 must be DDR6 and therefore AM6 socket.
Posted on Reply
#17
Makaveli
jesdalsWell if it ends up on AM5 it would also make AM5 a remarkable platform
Yes 16 core CCD with a 224mb Vcache will be the ultimate gaming chip on AM5.

And I would grab that after taking Zen 6 12 Core CCD 144mb vcache chip :)
user55616 cores per CCD will be needing faster DRAM. Zen7 must be DDR6 and therefore AM6 socket.
I agree the 24+ court count versions will need faster memory.

I however think you can get away with DDR5 on the 16 core model if it has a big cache on it.
Posted on Reply
#18
atomsymbol
user55616 cores per CCD will be needing faster DRAM. Zen7 must be DDR6 and therefore AM6 socket.
DDR6 won't be needed for a while because of L3 cache size+bandwidth+latency improvements in Zen6 and later CPUs. Performance in this context depends (1) on L3 cache size and (2) on inter-CCD latency. Zen6 dual-CCD CPU will effectively have 2*48 MiB L3 cache because of a much lower inter-CCD latency (potentially less than 40ns) - compared to Zen5 where inter-CCD L3 cache latency (~75ns) is actually bigger than DDR5-6000-CL30 memory latency (~70ns). For light-threaded workloads that like big caches (such as: games) Zen6 dual-CCD CPUs will most likely show a significant improment over Zen5 single-CCD CPUs, over Zen5 dual-CCD CPUs, and also over single-CCD Zen6 CPUs. In other words: a dual-CCD Zen6 CPU (2*48MiB L3 cache) can be expected to perform like Zen5 9800X3D (1*96MiB L3 cache) in gaming.
Posted on Reply
#19
mrnagant
_roman_Does amd really want to drop their advantage with avx512? that makes any intel processor as of now a better deal.
Read the article? "AVX10 unifies AVX-512 and AVX2 features"
Posted on Reply
#20
Legacy-ZA
Yes, it's time, I think I will upgrade soon, want to see some benchies and hopefully, some better memory prices. ^_^
Posted on Reply
#21
Random_User
FFS, Stop pushing the NPUs into the CPUs. Make it separate accelerator/chip. Better add a newer iGPU, with more CUs and efficiency, and CPU cores. Intel already wipes floor with all AMD APUs (except Halo series, which nobody can buy). Let alone the usual CPUs, which GPU performance is an utter joke.
Posted on Reply
#22
user556
MakaveliI however think you can get away with DDR5 on the 16 core model if it has a big cache on it.
That would be cool thing for AMD to do. Make Zen7 parts for both AM5 and AM6. Change the I/O die and voila!
Posted on Reply
#23
Battler624
Any idea if Zen 7 is gonna be on am5 or gonna move to am6?
Posted on Reply
#24
Buddyspike
atomsymbolDDR6 won't be needed for a while because of L3 cache size+bandwidth+latency improvements in Zen6 and later CPUs. Performance in this context depends (1) on L3 cache size and (2) on inter-CCD latency. Zen6 dual-CCD CPU will effectively have 2*48 MiB L3 cache because of a much lower inter-CCD latency (potentially less than 40ns) - compared to Zen5 where inter-CCD L3 cache latency (~75ns) is actually bigger than DDR5-6000-CL30 memory latency (~70ns). For light-threaded workloads that like big caches (such as: games) Zen6 dual-CCD CPUs will most likely show a significant improment over Zen5 single-CCD CPUs, over Zen5 dual-CCD CPUs, and also over single-CCD Zen6 CPUs. In other words: a dual-CCD Zen6 CPU (2*48MiB L3 cache) can be expected to perform like Zen5 9800X3D (1*96MiB L3 cache) in gaming.
But also Zen 6 high-end desktop variant is expected to have the additional 96MB v-cache(like the current 9800x3d etc.) and 12 cores per CCD , right?
Games rarely use more than 6 cores , and usually still bottlenecked by 1-2 main threads , anyway. On the other hand if intra-CCD latency penalty , thread synchronization etc. will be much faster than with 24 cores available on consumer CPUs more game engines will leverage more than 8 cores efficiently. For now only few simulator-like games can .
Posted on Reply
#25
Tek-Check
Random_UserFFS, Stop pushing the NPUs into the CPUs. Make it separate accelerator/chip. Better add a newer iGPU, with more CUs and efficiency, and CPU cores. Intel already wipes floor with all AMD APUs (except Halo series, which nobody can buy). Let alone the usual CPUs, which GPU performance is an utter joke.
Random user, random nonsense comment.
They are literally adding four extra big cores per CCD on Zen6 and then another four on Zen7.
user556That would be cool thing for AMD to do. Make Zen7 parts for both AM5 and AM6. Change the I/O die and voila!
They will have similar solution on EPYC Zen7, but most likely not on desktop. EPYC will have a separate memory die, the first time they split it from IOD.
JustBenchingZen 7 with 16 cores per CCD? That's nice, finally they are awake.
"Awake"? What does this even mean?
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