AMD is gearing up to introduce the "Zen 6" family of processors, with initial "Olympic Ridge" designs set to launch on the familiar AM5 socket. The company is staying true to its commitment to maintain socket compatibility across multiple generations, and Zen 6 is expected to follow suit. However, modern motherboards are increasingly equipped with larger BIOS ROM chips, moving from the standard 32 MB to 64 MB. Since the AM5 platform is intended to support several CPU generations, all the necessary microcode for various processors needs to be accommodated. This can lead to space constraints, and we've already seen some manufacturers drop support for older CPUs in newer BIOS versions to make room.

While companies have not been very clear about the reasons for this change, they often use marketing phrases like "Future CPU Ready" or "Ultimate Compatibility." Notably, ASUS mentioned "Zen 6" support in their materials for the X870 AYW GAMING WIFI W, which is intriguing since AMD has not officially confirmed Zen 6 compatibility with AM5. Over the weekend, a well-known hardware leaker, HXL, confirmed that both 600 and 800-series boards will support Zen 6, regardless of whether they have 32 MB or 64 MB BIOS chips. This is reassuring news. However, a lingering question remains: will manufacturers start dropping Zen 4 support on those 32 MB boards to make room, similar to what happened with first-generation Zen when Zen 3 launched on 16 MB boards? This is likely a significant concern for those purchasing motherboards now, and planning an upgrade later on when Zen 6 CPUs arrive.The Olympic Ridge generation will be a chiplet-based processor, similar to all AMD Ryzen desktop chips since the Ryzen 3000 series. These processors are anticipated to feature Zen 6 cores within CPU complex dies (CCDs) manufactured using TSMC's 2 nm N2 process. For the first time in these generations, AMD is expected to increase the CPU core counts per CCD. The chip is also likely to introduce a new client I/O die (cIOD), probably built on TSMC's 4 nm N4P node. This new cIOD is expected to have a significantly lower TDP compared to the current version built on 6 nm and will include an updated set of DDR5 memory controllers that support higher speeds.