Monday, November 3rd 2025
More Evidence for AVX10 and APX Support in Intel "Nova Lake" Emerge
Intel's advanced features like AVX10, APX, and AMX instruction sets—designed for 512-bit acceleration and fast vector/matrix multiplication for tasks such as content creation, encoding/decoding, and AI—may not be exclusive to Intel Xeon processors. We could potentially see them in consumer "Nova Lake" processors. According to the Netwide Assembler (NASM), an assembler for the x86 CPU, Nova Lake might introduce these features in consumer PCs once again. A few weeks ago, it was believed that Nova Lake wouldn't include any of Intel's advanced x86 extensions. The latest GCC compiler patch indicated that the initial Nova Lake enablement does not incorporate AVX10, AMX, or APX. This suggested that support for these new x86 instructions might be absent from the next-generation CPU.
Initially, Intel chose to disable AVX-512 for the "Alder Lake" and "Raptor Lake" client-oriented CPU lineups, meaning that only server-grade Xeon CPUs benefited from the accelerated 512-bit data paths. With the release of NASM 3.0 and its subsequent 3.1 update, we are once again optimistic that Nova Lake will bring 512-bit acceleration to its client CPUs. Rumored to feature up to 52 cores, including 16 P-Cores, 32 E-Cores, and 4 LPE-Cores, Nova Lake could be an ideal CPU for gaming and workstation tasks, covering a wide range of scenarios and workloads, except for server applications, which are reserved for Xeon. Additionally, it could take advantage of the extensive ecosystem of AVX-accelerated software available today.
For reference, AMD introduced full AVX-512 support with its "Zen 5" cores across its product range, providing a performance boost in optimized applications for both desktop and server CPUs. This marked the first time AMD did not emulate 512-bit AVX, which previously required splitting 512-bit data into two 256-bit units to be processed over two cycles. If Intel reintroduces full AVX-512 acceleration in its client SoCs, it will mark the first time both companies offer 512-bit vector acceleration in their consumer CPUs simultaneously.
Source:
@InstLatX64 on X
Initially, Intel chose to disable AVX-512 for the "Alder Lake" and "Raptor Lake" client-oriented CPU lineups, meaning that only server-grade Xeon CPUs benefited from the accelerated 512-bit data paths. With the release of NASM 3.0 and its subsequent 3.1 update, we are once again optimistic that Nova Lake will bring 512-bit acceleration to its client CPUs. Rumored to feature up to 52 cores, including 16 P-Cores, 32 E-Cores, and 4 LPE-Cores, Nova Lake could be an ideal CPU for gaming and workstation tasks, covering a wide range of scenarios and workloads, except for server applications, which are reserved for Xeon. Additionally, it could take advantage of the extensive ecosystem of AVX-accelerated software available today.
36 Comments on More Evidence for AVX10 and APX Support in Intel "Nova Lake" Emerge
Sources of the photos:
chipsandcheese.com/p/skylake-intels-longest-serving-architecture
Compression/decompression and crypto tasks also can make use of AVX-512 for some extra gains, and those take place in lots of places.It used to be really bad in terms of throttling and power consumption, but newer implementations basically solved that, see:
www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/#throttling
AVX-512 actually uses less power than regular AVX and SSE, mostly due to throttling, but still manages to finish the tasks way faster.
Here's a longer writeup on Zen 5's AVX-512 behaviour:
chipsandcheese.com/p/zen-5s-avx-512-frequency-behavior
Intel's current AVX-512 implementations have also pretty much solved the power and throttling issues.
It's a common misconception that AVX512 is only relevant for special workloads or for its wider 512-bit registers. But AVX512 introduced a lot more instructions that are beneficial for all sorts of (smaller) use cases and also work on (double the number of) 128 and 256-bit registers, and if you don't use 512-bit operations, there's no throttling and it's just as—if not more—efficient as AVX2. With modern implementations there's no longer a frequency penalty like there used to be with older Intel CPUs, so there's basically no downside in using AVX512.
By now, the main thing still holding it back is the lack of widespread hardware support and the need to support older hardware still.
I imagine that when certain technologies are developed jointly by both companies (AMD and Intel), the CPUs from both companies are released with the new technologies simultaneously, without either having priority over the technology's usage time.
Some of you probably remember Alder Lake initially shipped with AVX-512 support enabled, and from what I can gather Intel originally intended for this to be handled in software. Unsurprisingly this didn't work flawlessly, leaving them the only option to disable it (although they could have left us the option…), and from what we've seen in recent AVX10.2 documentation they now plan to use the double-pumped approach for E-cores (also used by VIA and AMD). So why did Intel require so many generations fix this "defect"? Raptor Lake and Arrow Lake was already too far along in their development by the time they realized their mistake.As well as mobile Tiger Lake and Ice Lake, assuming we're not counting workstation chips.