Monday, November 3rd 2025
More Evidence for AVX10 and APX Support in Intel "Nova Lake" Emerge
Intel's advanced features like AVX10, APX, and AMX instruction sets—designed for 512-bit acceleration and fast vector/matrix multiplication for tasks such as content creation, encoding/decoding, and AI—may not be exclusive to Intel Xeon processors. We could potentially see them in consumer "Nova Lake" processors. According to the Netwide Assembler (NASM), an assembler for the x86 CPU, Nova Lake might introduce these features in consumer PCs once again. A few weeks ago, it was believed that Nova Lake wouldn't include any of Intel's advanced x86 extensions. The latest GCC compiler patch indicated that the initial Nova Lake enablement does not incorporate AVX10, AMX, or APX. This suggested that support for these new x86 instructions might be absent from the next-generation CPU.
Initially, Intel chose to disable AVX-512 for the "Alder Lake" and "Raptor Lake" client-oriented CPU lineups, meaning that only server-grade Xeon CPUs benefited from the accelerated 512-bit data paths. With the release of NASM 3.0 and its subsequent 3.1 update, we are once again optimistic that Nova Lake will bring 512-bit acceleration to its client CPUs. Rumored to feature up to 52 cores, including 16 P-Cores, 32 E-Cores, and 4 LPE-Cores, Nova Lake could be an ideal CPU for gaming and workstation tasks, covering a wide range of scenarios and workloads, except for server applications, which are reserved for Xeon. Additionally, it could take advantage of the extensive ecosystem of AVX-accelerated software available today.
For reference, AMD introduced full AVX-512 support with its "Zen 5" cores across its product range, providing a performance boost in optimized applications for both desktop and server CPUs. This marked the first time AMD did not emulate 512-bit AVX, which previously required splitting 512-bit data into two 256-bit units to be processed over two cycles. If Intel reintroduces full AVX-512 acceleration in its client SoCs, it will mark the first time both companies offer 512-bit vector acceleration in their consumer CPUs simultaneously.
Source:
@InstLatX64 on X
Initially, Intel chose to disable AVX-512 for the "Alder Lake" and "Raptor Lake" client-oriented CPU lineups, meaning that only server-grade Xeon CPUs benefited from the accelerated 512-bit data paths. With the release of NASM 3.0 and its subsequent 3.1 update, we are once again optimistic that Nova Lake will bring 512-bit acceleration to its client CPUs. Rumored to feature up to 52 cores, including 16 P-Cores, 32 E-Cores, and 4 LPE-Cores, Nova Lake could be an ideal CPU for gaming and workstation tasks, covering a wide range of scenarios and workloads, except for server applications, which are reserved for Xeon. Additionally, it could take advantage of the extensive ecosystem of AVX-accelerated software available today.
36 Comments on More Evidence for AVX10 and APX Support in Intel "Nova Lake" Emerge
Does that mean "emulating" ABX-512 in author's view?
The documents quoted in that tweet (Intel® Advanced Vector Extensions 10.2 (Intel® AVX10.2) Architecture Specification version 5.0and The Converged Vector ISA: Intel® Advanced Vector Extensions 10 Technical Paper version 3.0) do not mention Nova Lake by name either.
Edit: maybe there are unpublished versions of those documents supporting this rumor, in that case we'll see it as soon as Intel publishes them.The latest AVX10.2 specification removed 256-bit-only mode, so every core supporting AVX10.2 will do 512-bit. The question is whether Nova Lake will support it. According to Intel's changes to the GCC compiler it won't.
e cores are small because they don't have that.
Jim Keller had the idea of a "royal core" basically a setup where a bunch of e-cores would be combined to act like one big core which could process large instructions like AVX in one go.
stuff didn't pan out that way. now intel has e-cores and p-cores.
Not that it matters all that much, after all this time there still is very little consumer software that actually uses those massive instructions and most is running just fine on e-cores.
I read a few hours ago the stable release notes of gccIn the old days most instructions were split and executed over several cpu cycles. That is up to discussion to determine if zen4 has full avx-512 or not.
gcc.gnu.org/gcc-15/changes.htmlIntel can not make silicion with avx512. They do the workaround to make a worse not common instruction. So few packages already utilise avx512, this will not make it better. Other platform will get the advandage wiht such intel actions.
When they just "added" those features and just changing those features, it implies htey are years behind.
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It would be more news worthy to discuss those march=gfx1101 and how to utilise it and it potential. (I assume i remembered it correctly what i red yesterday)
The legacy 14 branch does not paint a better intel picture: gcc.gnu.org/gcc-14/changes.html
Anyways, just glad there will be competition for AMD.
It could have been the start of a new franchise from Blizzard.
Too much money from WoW screwed up all other projects from Blizzard, though. That's why it took another 10 years for Starcraft 2, Warcraft never got any RTS ever again except for a mediocre remaster, and Ghost got cancelled.
No Intel document he's quoting supports this, either.No image in his post contradicts Nova Lake missing AVX-512/AVX10.*, "portability across client, workstation and server CPUs" does not mean it happens in Nova Lake (maybe later), neither does "all Intel products" nor "Supported on P-cores, E-cores".
RPCS3, the PS3 emulator
Blender
SVT-AV1 (AV1 encoder)
The core design of Core and Xeon CPUs is the same; it's impossible to magically remove AVX-512 instructions in Core CPUs, since the core design is identical. That's why they are present in both the Xeon and Core lines, but they (and other server features) have been intentionally disabled in the Core line since 2015.
This and other arrogant decisions are the reason Intel is suffering huge losses today.
AVX-512 instructions should have been included in all x86 CPUs since 2015, in both Intel and AMD CPUs. Today, we should be discussing the implementation of the 4th generation of AVX-512 instructions, not the 1st.
AVX-512 in specific doesn't seem to be in the current situation Intel has because actual planified segmentation, but rather remnants of all the 10nm falling, bad management and stubborness of it to release actually evolved main architecture designs in 14nm and so and so. Though the final result is the same in a segmented support for AVX-512 in consumer segments products because of the whole mess situation that happened with Intel and that AMD took a while to support it and none supported them on the consumer segments at the same time as a result.
And it's not like the supporting hardware is sitting idle wasting die space.
other extensions make use of the infrastructure in place that could do avx512.
There is hardly any popular software that uses avx512, intel made the right move disabling it if that was the thing that was causing issues on 12th gen alderlake.
it would have been better if they offered p core only chips that did do avx 512 for the fans.
No one cared for avx512 when they were available, linus (torvalds) shat upon it when it was still around.
www.phoronix.com/news/Linus-Torvalds-On-AVX-512
Intel tried...
Intel did a lot of things wrong, scrapping avx512 which would have melted wires in your home for raptor lake while it's getting it's act together isn't one of them.
opensearch.org/blog/boost-opensearch-vector-search-performance-with-intel-avx512/
community.intel.com/t5/Blogs/Tech-Innovation/Artificial-Intelligence-AI/Unleashing-AI-s-Potential-Exploring-the-Intel-AVX-512/post/1567181
And if you don't have the time to spend for that, then you'd just make use of compiler optimizations to do stuff for you, which would be the low-hanging fruit here.
Part of the reason the core design is different is also because the first implementation of avx-512 was an extension of their cpu-as-a-gpu project called Knights Landing (which is where the mesh topography came from) and extremely experimental. the massive dual execution units take up a large amount of the die area and required very beefy power delivery to keep the ridiculous number of transistors active, which meant that they downclocked heavily when avx-512 was active.
There is very little software that takes advantage of these instructions, and half of that software is also heavily dependent on the implementation because the first generation of chips was basically geared toward research use.
That leaves Rocket Lake (11900K) and Ryzen 7000/9000 as the only client segment CPUs that can support it in some form.