PCI-SIG has released a small update on its upcoming PCIe 8.0 standard, with the draft milestone reaching version 0.5. Perhaps the most intriguing aspect of this draft update is not the performance itself, but the exploration of a new connector technology to support this high-bandwidth protocol. Last year, we learned that PCI-SIG plans to implement a 256.0 GT/s raw bit rate and 1 TB/s of bidirectional bandwidth in the x16 lane configuration. We had assumed that the protocol would continue using the familiar connector technology seen in previous PCIe updates. However, it turns out that the current connector might be a limiting factor, prompting the search for a replacement for the traditional PCIe electrical connection.

The traditional PCIe connector is a copper-based link with up to 16 lanes connecting graphics cards to a slot. In a full x16 lane configuration, the PCIe generation supported by the motherboard provides the best performance, offering the maximum bandwidth the platform can deliver. However, with a 256 GT/s raw bit rate, the connector provides about 1 TB/s of bidirectional bandwidth, which is eight times faster than the current PCIe 5.0 platform used with modern GPUs and CPUs. This indicates that the current physical layer facilitating communication between a GPU and a motherboard is nearing saturation with the advent of PCIe 8.0, necessitating the consideration of an alternative connection method.PC enthusiasts need not worry, as the standard is on track for final installment by 2028, suggesting that consumer PCs will likely adopt it in the next decade. Consumer GPUs have only recently transitioned from PCIe 4.0 to PCIe 5.0, with NVIDIA moving to PCIe 5.0 in the RTX 50-Series "Blackwell" from PCIe 4.0 in the RTX 40-Series "Ada Lovelace." This means that by the time consumer GPUs require PCIe 8.0, the entire ecosystem will likely adapt seamlessly in the following years. Initially, only server GPUs are expected to adopt this standard when AMD, Intel, and NVIDIA transition to the new standard. Below are some design goals that PCIe 8.0 aims to achieve in the final v1.0 specification:

• Delivering a 256.0 GT/s raw bit rate and up to 1.0 TB/s bidirectionally via x16 configuration
• Evaluating new connector technology
• Ensuring latency, FEC, and reliability targets are met
• Maintaining backward compatibility with previous generations of PCIe technology
• Improving bandwidth through protocol enhancements
• Reducing power consumption through additional techniques