Samsung has reportedly raised prices for several DDR5 memory modules by up to 60% this month as supply tightens amid the global push to build AI data centers, according to two people familiar with the changes. The increases follow Samsung's unusual move to delay October contract pricing, which it normally sets each month. The jump in server-grade DDR5 costs is putting added pressure on hyperscalers and OEMs already short on parts. Fusion Worldwide president Tobey Gonnerman told Reuters that many major server builders "now accept that they won't get nearly enough product," with premiums reaching "extreme" levels. Recent contract pricing shows how fast costs have climbed. Samsung's 32 GB DDR5 module price rose from $149 in September to $239 in November. The company also raised prices for 16 GB and 128 GB DDR5 modules by about 50%, to $135 and $1,194. Prices for 64 GB and 96 GB modules increased by more than 30%, sources said.

The shortage has triggered panic buying for some customers and is disrupting demand for other semiconductor parts. Semiconductor Manufacturing International Corporation (SMIC) said the tight DDR5 market has caused buyers to hold back orders for additional chip types, while Xiaomi warned that rising memory prices are pushing up smartphone production costs. The shortage is turning into an advantage for Samsung. While the company still trails rivals in advanced AI processors, its memory division now has stronger pricing leverage than SK Hynix and Micron. TrendForce expects Samsung's contract prices to rise 40-50% in Q4, higher than the roughly 30% increase forecast for the broader market, supported by strong demand and long-term supply deals running into 2026 and 2027.

Just three days ago, NVIDIA and TSMC celebrated the production of the first "Blackwell" GPU at TSMC's Fab 21 complex in Phoenix, Arizona. This marked a significant milestone for both companies, as it signifies the creation of the world's most powerful silicon on U.S. soil. However, the production phase is only part of the story, as the chip benefits not only from an advanced node but also from TSMC's advanced packaging systems. Specifically, the Blackwell family of GPUs utilizes TSMC's Chip on Wafer on Substrate (CoWoS) packaging system.

For CoWoS access, TSMC must send these chips back to the Taiwanese facilities overseas and house the raw die in a CoWoS-S configuration with silicon interposer. This establishes a supply chain dependency on Taiwanese facilities, which remain essential for completing the production of advanced silicon. As a result, the chip isn't entirely manufactured on American soil, indicating that some issues still need to be resolved. TSMC produces NVIDIA's Blackwell chips using a custom 4N 4 nm class node specifically designed for NVIDIA. This die is paired with eight stacks of HBM3E, all housed within a CoWoS-S package.

SiPearl, the European fabless designer of sovereign high-performance energy-efficient processors for HPC, AI and data centers, today announced the launch of the Athena1 processor for dual-use applications.

Based on the unique expertise in Europe developed for the design of Rhea1 (SiPearl's first generation processor, dedicated to HPC), Athena1 will offer features specifically tailored to the workloads of government, defense and aerospace applications. These include, for example, secure communications and intelligence, cryptography and encryption, intelligence processing, tactical networks, electronic detection or local data processing on vehicles.

After last week's leak of an EA buyout, an official agreement was announced that would see the game studio be bought out by PIF, Silver Lake, and Affinity Partners for a whopping $55 bn, with the current CEO, Andrew Wilson, remaining in his post for the time being. The deal is slated to go into effect in Q1 FY2027, pending shareholder and regulatory approvals. A subsequent report by The Financial Times, however, has provided slightly more details about the future of EA under its new ownership.

According to the new report, investors are banking on using AI to cut EA's operating costs and "manage a large debt load," indicating that we may see a drastic shift to the inclusion of AI in games, where it may replace developers and actors, although it is so far unclear exactly how EA and its new owners plan to leverage AI in the company's projects. This news comes mere months after the United Videogame Workers Union was founded, partially in response to the rise of artificial intelligence in gaming and mass layoffs that have plagued the gaming industry of late.

At the 2025 Global Memory Innovation Forum in Shenzhen, China, Samsung confirmed it will ship its next-generation CXL 3.1 and PCIe 6.0 CMM-D storage products. Kevin Yoo, Samsung's Memory BU CTO, outlined a practical timeline for the company's upcoming storage solutions. The PM1763 Gen 6 SSD is expected to launch in early 2026, offering about twice the performance of its predecessor while maintaining power consumption around 25 watts. Following the release of 256 TB Gen 5 drives in 2026, Samsung plans to introduce a 512 TB PCIe Gen 6 unit around 2027 in the 1T EDSFF format. Additionally, a seventh-generation Z-NAND with GIDS, referred to as memory-class storage, is scheduled for 2026.

Samsung had previously showcased its PM1763 256 TB SSD at the Future of Memory Storage 2025 event in August. The company first demonstrated a working prototype of the 256 TB unit, initially hinted at in 2023. However, at the FSM event, it was revealed that the SSD is nearing readiness for market release. With a completely redesigned capacitor, controller, and DRAM layout, it appears Samsung is focusing on optimizing cooling and performance efficiency for these high-capacity drives. High-capacity SSDs are of significant interest to AI labs, especially as data requirements for training continue to grow. The exact timelines and release dates of these SSDs is unknown, and Samsung may change specific date as it irons out any remaining power/thermal issues it encounters in these high-capacity drives.

TSMC is the only semiconductor maker to move its nodes at incredible speeds from design to mass production. According to Taiwanese media outlet Taipei Times, TSMC is expected to lay the groundwork for Fab 25, a multiphase manufacturing complex planned in Taichung's Central Taiwan Science Park. Company officials say construction will begin in the Q4 of this year and that the first of four planned factories could be finished by 2027, setting the stage for commercial A14 chip production by the end of 2028. The initial funding is large but only as TSMC has prepared 500 billion NTD, roughly $16.38 billion, for the first stage, with many more billions expected as the full site is built out. This push is intended to bring capacity online sooner than anticipated, so customers don't experience any delays.

TSMC executives have denied recent rumors that packaging or U.S. projects are forcing delays to the Taiwan buildout. Technical and operational planning is designed to reduce risk and accelerate volume. TSMC plans to seed A14 production earlier at Phases 3 and 4 of Fab 20 near its Hsinchu R&D campus, while Fab 25 will eventually serve as a dedicated high-volume home for the node. The initial A14 rollout will follow conventional process improvements, with a succeeding A14 Plus or A14P revision expected to introduce additional improvements. Still, advanced packaging remains the tightest constraint for the industry, and a lasting balance between supply and demand is unlikely to appear anytime soon.

ASML is about to manufacture significantly more Low-NA EUV and High-NA EUV machines than it originally anticipated. As you may be aware, acquiring an EUV scanner is a year-long process, during which companies make commitments that can span several years to procure these tools. According to ASML, the company estimates that in 2027, based on current order information and demand, it will deliver 56 Low-NA EUV scanners. This includes five units for Intel, seven units for Samsung, and as many as 20 units for SK Hynix. According to South Korean media, SK Hynix plans to install 20 Low-NA EUV units in the next two years, all designed for HBM memory and advanced storage solutions.

For High-NA, ASML plans to deliver 10 High-NA EUV scanners, each costing around $380 million. Intel will add to its facilities manufacturing the 14A node, and SK Hynix is expected to use two of those as well for its memory operations. Intel is betting big on its next-generation 14A node, adding additional EUV tools to its already existing High-NA portfolio. In the past, Intel disclosed that it processed over 30,000 wafers within a single quarter while achieving simplified manufacturing by cutting the required steps for a particular layer from 40 to fewer than 10, which naturally led to much faster cycle times. Similarly, Samsung has seen impressive results in its operations, documenting a 60% reduction in cycle time for one of its specific applications.

TSMC is reportedly handling a significant volume of orders, with 15 or more customers designing on its latest "N2" 2 nm node. According to KLA's Ahmad Khan and Bren Higgins, this N2 node is attracting considerable interest, with 10 of these customers focused on high-performance computing (HPC) designs. Potential clients could include Intel, NVIDIA, AMD, and various startups, while the rest may be developing mobile-optimized designs from companies like Apple, Qualcomm, and MediaTek. "As we're seeing today, the N2 node has about 15 customers working on designs, with around 10 focused on high-performance computing. This is driving rigorous performance requirements," noted KLA's team at a Goldman Sachs conference.

TSMC's N2 node is noted for its high power efficiency and a transistor density of 236.17 million transistors per mm², making it an excellent choice for both HPC/AI and mobile designs. Although TSMC initially planned to implement a backside power delivery network with this node, this feature has been shifted to the A16 node. The N2 will remain a Gate All Around (GAA) FET design to better control transistor gate leakage, moving away from the older FinFET design that has reached its limits with further miniaturization. TSMC has scheduled the commercial launch of the N2 semiconductor node for the second half of 2026, indicating that major technology companies may start adopting this advanced chip technology by early 2027.

NVIDIA is preparing a significant change in its chip strategy for its next-generation GPU design, codenamed "Feynman", as the first customer of TSMC's A16 process. This choice breaks NVIDIA's long-running pattern of adopting slightly older nodes to extract greater efficiency and performance gains for its datacenter accelerators. NVIDIA's biggest AI dies are enormous, at 104 billion transistors currently per each "Blackwell Ultra" die and occupying areas that are breaking reticle limits. Such a scale typically favors one or two generations old nodes to protect yield and thermal characteristics. To keep up with the compute demand, NVIDIA appears to be adapting its architectures to A16 while keeping other families like "Rubin" on refined N3P variants and paired with CoWoS-L packaging.

The most appealing aspect of the A16 node will be its backside power delivery, which separates power and signal routing to reduce losses and simplify floor planning. Implementations range from buried power rails that still use a front-side lowest metal layer to power vias that reach the rear side. TSMC's Super Power Rail concept enables power to be delivered directly to the transistor's source and drain terminals, resulting in lower resistance. Those choices affect efficiency, layout, and thermal behavior. Power demands for high-end AI accelerators are rising fast. Current flagship solutions already draw about 1,400 W in Blackwell Ultra, and next-generation Rubin designs are expected to exceed 2,300 W. Hence, node selection will be critical for the next-generation Feynman design, given its multi-gigawatt power requirement. If A16 reaches volume production on schedule, first silicon could arrive in late 2027 or early 2028.

While AMD hasn't launched its upcoming Instinct MI400 series of accelerators yet, the company has started preparing its supply chain for what comes after. Thanks to SemiAnalysis, we have a clearer picture of what AMD's Instinct MI500 UAL256 rack will look like. At the base of each compute node, there will be a single "Verano" CPU paired with four Instinct MI500 accelerators. With up to 64 nodes, split across two 32-node racks, AMD plans to enable 256 logical GPUs and 64 CPUs per mega pod, working in tandem for advanced AI and HPC workloads. Instinct MI500s UAL256 will be AMD's second-generation rack-scale system, following the upcoming Instinct MI450X IF128 aka "Helios", scheduled for the second half of 2026. The Instinct MI500 UAL256 scale-up mega pod is scheduled to arrive in 2027, just in time for Verano and Instinct MI500 accelerator.

The Instinct MI500 UAL256 scale-up mega pod splits the compute into two 32-rack cabinets, with a single central rack connecting them and hosting 18 switching trays for networking. Each of these networking trays contains four 102.4T "Vulcano" switch ASICs, designed for 800G external throughput, and manufactured on TSMC's 3 nm node. For the central processor, AMD showed few details at its Advancing AI event, which claimed that Verano introduces the "Zen 7" microarchitecture for even higher IPC and support for even newer instruction sets. For now, it's not clear if AMD will increase CPU core counts beyond the up to 256 cores per package of "Venice." Still, we're hearing that Verano will retain the Socket SP7 infrastructure, which means it will likely retain the memory and PCIe interfaces introduced in 2026, such as PCIe Gen 6, UALink, and Ultra Ethernet.

According to Korean analyst Kurnal on X, Rapidus, the Japanese foundry pushing into leading-edge chips, will deliver its upcoming 2 nm process, called 2HP, with a transistor density that rivals the best in the business, even TSMC. The reporting allegedly shows a logic density of 237.31 million transistors per square millimeter for 2HP, essentially matching TSMC's N2, which has 236.17 MTr/mm², and comfortably ahead of Intel's 18A at about 184.21 MTr/mm². Rapidus has focused on high-density standard cells and a single-wafer front-end method that allows engineers to tune runs before scaling. It states that a 2 nm gate-all-around test chip built with ASML EUV tools met its electrical targets. The firm plans to publish process design kits in early 2026 and aims to start high-volume production at its IIM-1 facility in 2027, with monthly output expected to reach roughly 25,000 wafers.

What Rapidus is selling beyond raw density is speed and flexibility. While being a node or two behind TSMC in 2027, the company promises significantly shorter cycle times than traditional batch processes, reducing the typical turnaround from around 120 days to approximately 50 days, and offering extreme "hot lot" pushes down to 15 days for urgent orders. To deliver this, Rapidus is building a custom backend ecosystem with OSATs, EDA vendors, IP providers, and materials partners, and it benefits from government support and interest from major compute players. However, density is only one metric of the new node. Energy efficiency, performance per watt, mature supply chains, and, crucially, repeatable yields will determine whether Rapidus can turn validated test silicon into a reliable, high-volume competitor.

TSMC has quietly accelerated the start of construction on a large new complex designed to produce 1.4 nm wafers, ramping up plans for a multi-building site known as Fab 25. The facility, which will be located in the Central Taiwan Science Park near Taichung, is expected to include four production buildings and carries an initial investment estimate in the low-trillion New Taiwan dollar range. TSMC aims for the first plant to begin risk production by the end of 2027 and for high-volume production to ramp up in the second half of 2028 for major customers, mainly Apple, NVIDIA, AMD, and others. Suppliers of equipment and construction materials have been notified to accelerate their deliveries, ensuring that specialized tools and materials arrive at on a shorter schedule.

TSMC expects the Angstrom-era node to deliver more than 15% performance gains and significant power reductions, reportedly up to 30%. Customers can also expect substantially higher wafer costs compared to the 2 nm node, given the node's complexity and higher operational costs. The buildout also addresses infrastructure issues, with regulators and the company negotiating commitments for recycled water and desalination to protect local supplies. Some Hsinchu facilities are being refitted to host pilot lines and R&D work that will support the 1.4 nm program, and regional planning in the south is already contemplating future fabs for even smaller nodes. If TSMC meets this accelerated timeline, Fab 25 will further extend the foundry's lead and reshape the capital intensity and competitive dynamics of advanced chipmaking.

A pair of leaked partner roadmaps shared by hardware leaker @momomo_us suggests modest change for laptop processors through 2026, followed by a clearer shift in 2027. The documents indicate that AMD will largely be on autopilot next year, with a Zen 5-based refresh called Gorgon Point, which appears to reuse the same core counts, the same 4 nm node, and most of the same NPU and graphics building blocks as Strix Point. That implies only a slight performance improvement, likely due to tighter tuning rather than a new architecture. As a result, high-end mobile parts, such as the Fire Range and the Strix Halo APU, may see little to no refresh in 2026. Zen 6 is coming in 2026 for desktop and server, but for the mobile segment, another year of waiting is on the table.

The leak becomes more interesting for 2027, where two Zen 6 families appear: Gator Range and Medusa Point. Gator Range is positioned as the future elite mobile family and is likely to replace Fire Range; however, the roadmap provides no in-depth technical details beyond the move to Zen 6. Medusa Point is described more concretely. It is said to utilize the FP10 package, be manufactured on a 3 nm process, and ship as a monolithic APU that combines different core types and features stronger iGPU. The listing mentions four full Zen 6 cores, four compact Zen 6c cores, two low-power cores, and roughly eight RDNA / UDNA EUs for on-chip graphics. If true, Medusa Point would target premium laptops with a balance of CPU compute and capable iGPU for gaming and local AI processing. As always with leaked roadmaps, expect changes and wait for official confirmations from AMD.

According to market reports, NVIDIA is planning to develop its own High Bandwidth Memory (HBM) Base Die design, with production targeting 3 nm process technology and trial manufacturing expected to begin in late 2027. TrendForce, citing Commercial Times, sees this as a strategic move that would allow NVIDIA to control the underlying logic components of HBM modules regardless of which memory manufacturer supplies the stacked memory layers. The news disrupted the HBM industry, where SK Hynix currently dominates. While SK Hynix uses primarily in-house Base Die solutions, it relies on advanced manufacturing processes from companies like TSMC to achieve speeds above 10 Gbps. Memory manufacturers typically lack the complex design capabilities needed for sophisticated Base Die and ASIC development.

NVIDIA's plan seems to aim at tightening its grip on its ecosystem through the NVLink Fusion platform giving customers more mix-and-match choices. However, cloud service providers might push back against NVIDIA's Base Die solutions, as many first went for ASIC development to cut their reliance on NVIDIA. At the same time, SK Hynix keeps pushing its HBM4 technology forward. The company just recently shipped 12-layer samples with 36 GB capacity and speed over 2 TB per second (60% faster than HBM3E). HBM4 is expected to deliver higher speeds and stacking with more complex packaging integration. As we previously reported, NVIDIA and AMD will deploy customized HBM4 memory in their upcoming AI accelerators. Combined with NVIDIA's plans to manufacture its own HBM Base Die and SK Hynix's accelerated HBM4 production timeline, the HBM market is about to enter a new phase of competition and change.

According to the technology analyst firm, Gartner, we learned this week that hosted desktops, known as Desktop-as-a-Service (DaaS), are now often less expensive to operate than traditional laptops and are expected to become cost-effective for most employees within two years. That could force many enterprises to invest more in DaaS rather than their local PC infrastructure. In its Magic Quadrant for DaaS, Gartner forecasts that by 2027, approximately 20% of workers will use a cloud-hosted machine as their primary workspace, up from around 10% in 2019. The firm also expects DaaS to be cost-effective for approximately 95% of use cases/roles by 2027, compared with roughly 40% in 2019. Gartner cites lower total cost of ownership as a key factor, especially when organizations pair DaaS with light, inexpensive thin-client endpoints. New deployments are increasingly cloud-first, and many firms are choosing hosted solutions over building or expanding on-premises virtual desktop infrastructure. Especially with AI buildout requiring expensive GPUs, it could be more viable for enterprises to use a hosted acceleration when needed, instead of buying expensive hardware for local processing.

The report shows several market leaders and practical questions for IT teams. Microsoft is named the standout vendor for its wide cloud reach, workplace tools, and AI features, though buyers are advised to consider the differences between Windows 365 and Azure Virtual Desktop. Citrix is praised for its strong management and protocol technology, but is warned for offering bundled packages and long subscription terms. Omnissa is recognized for scalable offerings, while some customers worry about global support. AWS earns credit for integrating management tools into Workspaces. Beyond vendor rankings, experts highlight a new use case that could transform desktop strategy. As AI tools and autonomous agents begin to handle routine computer tasks, they will likely need their own optimized virtual workspaces. That raises questions about how those spaces will be designed, secured, and licensed. However, the takeaway is clear: budget planning, procurement, and desktop strategy must adapt to recurring cloud costs, endpoint choices, and a future where both people and software agents coexist in the digital workplace.

TSMC will retire its smallest wafer line and reorganize several legacy fabs in Hsinchu as part of a cost and efficiency drive. TSMC plans to discontinue production on 6-inch 150 mm wafers within two years and consolidate its 8-inch 200 mm capacity, enabling machines and staff to operate more efficiently. The company has begun winding down its gallium nitride foundry services, which relied on some 200 millimeter lines, and will repurpose the affected buildings for other production or research purposes. Taiwanese media identify Fab 2 and Fab 5 among the sites expected to stop regular production by 2027. TSMC says it will work with customers to migrate production to nearby 200 millimeter facilities and to encourage longer-term moves to larger 300 millimeter processes in its gigafabs, where volume economics are stronger.

The business reasoning is very simple. Smaller wafers yield far fewer dies per cycle and cannot match the economics of modern nodes designed for AI and other high-performance markets. By consolidating older lines, the company can free capital and talent to expand advanced node capacity and increase utilization at larger fabs, including the long-operating Fab 12 and the new construction across the street. Some 200 mm factories will absorb displaced work, depending on their equipment and customers' decisions. For suppliers and product teams, the change means negotiated ramp schedules, possible redeployment of tools, and a shorter runway for products based on 150 mm platforms.

NVIDIA's and AMD's next-generation accelerators will definitely utilize a next-generation HBM4 memory, too. However, interesting news, confirmed by SemiAnalysis, is that these accelerators will utilize a customized HBM memory for the first time. In an HBM stack, consisting of stacked DRAM dies up to a 12-high, connected with TSVs, there is the possibility of embedding an optional base die with customized logic/accelerator circuitry tailored to a specific need. It appears that NVIDIA and AMD are not only exploring this option to gain more performance, but are also actively working on an implementation with a custom base that will push these accelerators ahead of any third-party ASIC solution by a third. Since everyone is trying to grab a bit of market share in the AI ASIC world, NVIDIA and AMD have to innovate their designs to stay ahead constantly.

"We expect NVIDIA and AMD to come out with their custom HBM implementations with HBM4, with other accelerator designers likely to only have a custom base die implementation by HBM4E in the 2027 timeframe," notes the SemiAnalysis post. This means that while ASIC designers, such as Broadcom and MediaTek, will have a working solution in 2027 chips, NVIDIA and AMD will have a working custom HBM4 in 2026 products. For NVIDIA, this is the "Rubin" architecture, supposed to outperform the current "Blackwell" implementation by a wide margin. For AMD, this is the Instinct MI400 series of accelerators, which is coming for the first time in a rack-scale flavor.

Electronic Arts today announced preliminary financial results for its first quarter ended June 30, 2025.

"We delivered a strong start to FY26, outperforming expectations ahead of what will be the most exciting launch slate in EA's history," said Andrew Wilson, CEO of Electronic Arts. "From deepening player engagement in EA SPORTS to gearing up for Battlefield 6 and skate., we're scaling our global communities and continuing to shape the future of interactive entertainment."

Apple is preparing to release a major update for its Vision Pro headset before the end of the year. Inside, the current M2 chip will be replaced by the newer M4 SoC, built on a 3 nm process from TSMC. That extra shrink brings noticeably better CPU and GPU performance and a more capable neural engine, so you'll see smoother AI-powered features right on the headset. Apple hasn't stopped there, listening to early adopters and revamping the headband with softer padding and better balance to shift weight away from your face. At roughly 600 to 650 grams, the Vision Pro can feel heavy after only a few minutes, and this change should make longer sessions feel much more comfortable.

Behind the scenes, Apple is also working on a wired model called N107 for users who need rock-solid, low-latency connections to a Mac. Consider surgical training or complex CAD design, where even the slightest delay is unacceptable. If you're looking for something lighter and more affordable, Apple has that covered as well. A completely new Vision Pro, under the code name N100, is slated for 2027. By using slimmer lenses and lighter materials, it should shed several hundred grams without skimping on screen clarity or battery life. We expect to hear more about it as the Vision Pro 2 launch gets closer.

In just a few years, AMD has gone from the underdog to Intel's most serious challenger in the server world. Thanks to its EPYC processors, AMD now captures about a third of every dollar spent on server CPUs, up from essentially zero in 2017. Over that same period, Intel's share has slipped from nearly 100% to roughly 63%, signaling a significant shift in what companies choose to power their data centers. The real inflection point came with AMD's Zen architecture: by mid-2020, EPYC had already claimed more than 10% of server-CPU revenues. Meanwhile, Intel's rollout of Sapphire Rapids Xeons encountered delays and manufacturing issues, leaving customers to look elsewhere. By late 2022, AMD was over the 20% mark, and Intel found itself under 75% for the first time in years.

Looking ahead, analysts at IDC and Mercury Research, with data compiled by Bank of America, expect AMD's slice of the revenue pie to grow to about 36% by 2025, while Intel drops to around 55%. Arm-based server chips are also starting to make real inroads, forecast to account for roughly 9% of CPU revenue next year as major cloud providers seek more energy- and cost-efficient options. By 2027, AMD could approach a 40% revenue share, Intel may fall below half the market, and Arm designs could capture 10-12%. Remember that these figures track revenue rather than unit sales: AMD's gains come primarily from high-end, high-core-count processors, whereas Intel still shifts plenty of lower-priced models. With AMD poised to launch its Genoa and Bergamo EPYCs and Intel banking on the upcoming E-core Xeon 6 series to regain its footing, the fight for server-CPU supremacy is far from over. Still, Intel's once-unbeatable lead is clearly under threat.

Ark 2, the long-awaited sequel to Ark: Survival Evolved, was originally slated to launch as early as 2023, but it was later delayed to late 2024, and shortly after that deadline was missed, the Steam release date was simply changed to "to be announced." Now, however, the studio behind the Ark franchise, Studio Wildcard, says that it is optimistic for a 2027 launch. In an interview with PCGamesN, co-founders of the studio, Jesse Rapczak and Jeremy Stieglitz, said that the studio put Ark 2 on hold partially to make Ark Survival Ascended, which has helped the team further come to grips with Unreal Engine 5 and test out the new capabilities and technologies on offer from the new game engine.

"A small portion of our team continues to refine the mechanics of [Ark 2's] combat... It's very difficult to do soulslike combat in a multiplayer PvP context," says Stieglitz, adding that at least 18 months of focussed development work will be required to turn the existing content for Ark 2 into a playable early access game. Ark Survival Ascended has since launched in the meantime, and in the interview with PCGamesN, the game studio's executives say that it is still looking for the right time to pivot its development efforts from Ascended to Ark 2 without compromising the revenue stream generated by Ark Survival Ascended. Wildcard and prior Ark 2 trailers have made a number of ambitious promises when it comes to Ark 2, including a revamped traversal system, soulslike PVP combat, and a switch to third-person gameplay. The new game will also include NPC enemies—other than the wild beasts usually encountered in current Ark games—further complicating the development of the new game.

NVIDIA and Hewlett Packard Enterprise announced Tuesday at a supercomputing conference in Hamburg their partnership with Germany's Leibniz Supercomputing Centre to build a new supercomputer called Blue Lion which will deliver approximately 30 times more computing power than the current SuperMUC-NG system. The Blue Lion supercomputer will run on NVIDIA's upcoming Vera Rubin architecture. This setup combines the Rubin GPU with NVIDIA's first custom CPU Vera. The integrated system aims to unite simulation, data processing, and AI into one high-bandwidth low-latency platform. Optimized to support scientific research it boasts shared memory coherent compute abilities, and in-network acceleration.

HPE will build the system using its next-gen Cray technology by including NVIDIA GPUs along with cutting-edge storage and interconnect systems. The Blue Lion supercomputer will use HPE's 100% fanless direct liquid-cooling setup. This design circulates warm water through pipes for efficient cooling while the generated system's heat output will be reused to warm buildings nearby. The Blue Lion project comes after NVIDIA said Lawrence Berkeley National Lab in the US will also set up a Vera Rubin-powered system called Doudna next year. Scientists will have access to the Blue Lion supercomputer beginning in early 2027. The Blue Lion supercomputer, based in Germany will be utilized by researchers working on climate, physics, and machine learning. In contrast, Doudna, the U.S. Department of Energy's next supercomputer, will get its data from telescopes, genome sequencers, and fusion experiments.

WRC Promoter has confirmed that the publishing of games based on the FIA World Rally Championship will return to French publisher NACON. The agreement covers the development and publishing of the official WRC games and eSports competitions, granting NACON exclusive rights for PC and consoles for six seasons, from 2027 through 2032.

As part of this strategic partnership, NACON will begin development of an all-new WRC game series, aiming to deliver an immersive experience that faithfully reflects the reality of the championship and meets the expectations of both rally enthusiasts and new players. The games will feature the official rallies, vehicles, teams, drivers, and sponsors among the many anticipated content elements. This project represents a complete reboot of the franchise, based on an entirely fresh vision, and marks an ambitious new chapter in the brand's development.

Intel says its struggling Foundry division will finally break even in 2027, just as its advanced 14A process comes online. The announcement came during the J.P. Morgan Global Technology, Media & Communications Conference, where CFO David Zinsner outlined the plan to offset years of quarterly losses. Intel has been pouring billions of dollars into new fabs and equipment as it races to keep pace with TSMC and Samsung. Its first milestone is the 18A process, whose first product, codenamed Panther Lake, will arrive in client PCs late in 2025, with volume production following in 2026. Intel also plans to use 18A for its next Xeon "Clearwater Forest" server chips and offer it to a small set of external partners to prove the technology's readiness. "We have to start by using our own chips," Zinsner explained. "Once we show that Panther Lake and Clearwater Forest perform as expected, we'll see more interest from outside customers for 18A, 18A-P, and then 14A."

He acknowledged that initial adoption is low, but expressed confidence that proven performance will drive committed volume. A key part of the strategy is the use of High-NA EUV lithography at 14A. Zinsner admitted this will raise equipment costs at first, but he believes the improved transistor density and power efficiency will more than make up for the investment, boosting margins and factory utilization. Intel's path to break even also incorporates revenue from mature nodes such as Intel 16/12, advanced packaging services, and collaborations with UMC and Tower. Under its "smart capital" model, the company will balance internal wafer demand with third-party work, maintaining flexibility and cost discipline. With a relatively modest external revenue target (for a cash-bleeding foundry), low to mid single-digit billions per year, Intel Foundry aims to reach break-even in 2027 and move into sustained profitability soon afterward. By 2027, Intel 14A node and ehnaced the 1.8 nm-class 18A-P(T) node will also complement these break-even efforts.

Rumors about the recent cancelation of an unannounced Blade Runner project; following the alleged completion of a pre-production phase at Supermassive Games. Insider Gaming's "exclusive" article proposes that the UK-based computer game development studio had started work on a "character focused, cinematic, action adventure" around September 2024. An inside source disclosed a "Blade Runner: Time To Live" title, and a futuristic "New Zurich" setting—in 2065. The online publication has acquired "internal company documents" that apparently outlined a 10-12 hour single player campaign experience and a "compelling story blending the philosophical themes of Blade Runner, with kinetic action-adventure gameplay." Veteran members of Supermassive's "The Quarry" core dev team were reportedly involved in the IP's early-stage production cycle.

Insider Gaming outlined a surprising mix of internal details—sourced from their industry mole—suggesting that this project is/was not related to Alcon Interactive Group and Annapurna Interactive's still in-progress Blade Runner title. The report described some of Supermassive's key goals: "a full release was planned for September 2027 on PlayStation 5, Xbox Series X|S, PC, and the 'Gen 10' Xbox and PlayStation systems. It was set to have a full development budget of roughly $45 million with $9 million of it being used for external performance capture and acting talent. What wasn't included in the budget, however, was original music production, image rights and usage fees for performers, QA and game testing, localization, and any future DLC. As with any budget, the amount was subject to change as development got underway and costs rose or fell." The British company is still working on Directive 8020, an original premise sci-fi interactive adventure—presumably, nearing the end of full-blown production within the coming months.