Thursday, May 25th 2017

Samsung Announces Comprehensive Process Roadmap Down to 4 nm

Samsung stands as a technology giant in the industry, with tendrils stretching out towards almost every conceivable area of consumer, prosumer, and professional markets. It is also one of the companies which can actually bring up the fight to Intel when it comes to semiconductor manufacturing, with some analysts predicting the South Korean will dethrone Intel as the top chipmaker in Q2 of this year. Samsung scales from hyper-scale data centers to the internet-of-things, and is set to lead the industry with 8nm, 7nm, 6nm, 5nm, 4nm and 18nm FD-SOI in its newest process technology roadmap. The new Samsung roadmap shows how committed the company is (and the industry with it) towards enabling the highest performance possible from the depleting potential of the silicon medium. The 4 nm "post FinFET" structure process is set to be in risk production by 2020.

This announcement also marks Samsung's reiteration on the usage of EUV (Extreme Ultra Violet) tech towards wafer manufacturing, a technology that has long been hailed as the savior of denser processes, but has been ultimately pushed out of market adoption due to its complexity. Kelvin Low, senior director of foundry marketing at Samsung, said that the "magic number" for productivity (as in, with a sustainable investment/return ratio) with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable.
Samsung's newest foundry process technologies and solutions introduced at the annual Samsung Foundry Forum include:

8LPP (8nm Low Power Plus)
8LPP provides the most competitive scaling benefit before transitioning to EUV (Extreme Ultra Violet) lithography. Combining key process innovations from Samsung's 10nm technology, 8LPP offers additional benefits in the areas of performance and gate density as compared to 10LPP.

7LPP (7nm Low Power Plus)
7LPP will be the first semiconductor process technology to use an EUV lithography solution. 250W of maximum EUV source power, which is the most important milestone for EUV insertion into high volume production, was developed by the collaborative efforts of Samsung and ASML. EUV lithography deployment will break the barriers of Moore's law scaling, paving the way for single nanometer semiconductor technology generations.

6LPP (6nm Low Power Plus)
6LPP will adopt Samsung's unique Smart Scaling solutions, which will be incorporated on top of the EUV-based 7LPP technology, allowing for greater area scaling and ultra-low power benefits.

5LPP (5nm Low Power Plus)
5LPP extends the physical scaling limit of FinFET structure by implementing technology innovations from the next process generation, 4LPP, for better scaling and power reduction.

4LPP (4nm Low Power Plus)
4LPP will be the first implementation of next generation device architecture - MBCFETTM structure (Multi Bridge Channel FET). MBCFETTM is Samsung's unique GAAFET (Gate All Around FET) technology that uses a Nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture.

FD-SOI (Fully Depleted - Silicon on Insulator)
Well suited for IoT applications, Samsung will gradually expand its 28FDS technology into a broader platform offering by incorporating RF (Radio Frequency) and eMRAM(embedded Magnetic Random Access Memory) options. 18FDS is the next generation node on Samsung's FD-SOI roadmap with enhanced PPA (Power/Performance/Area). Sources: Samsung Newsroom, eeTimes
Add your own comment

6 Comments on Samsung Announces Comprehensive Process Roadmap Down to 4 nm

#1
CAPSLOCKSTUCK
Spaced Out Lunar Tick
Raevenlord
Kelvin Low
what a fantastic name.
Posted on Reply
#2
natr0n
Waiting for the annual comprehensive price fixing reports.
Posted on Reply
#3
HopelesslyFaithful
CAPSLOCKSTUCK
what a fantastic name.
must have had a name change or parents were geeks at minimum.
Posted on Reply
#4
Boosnie
paving the way for single nanometer semiconductor technology generations
I thought there was a quantum mechanical limit, not a technological limit, to the dimensioning of a gate.
Am I wrong?
Posted on Reply
#5
HopelesslyFaithful
Boosnie
I thought there was a quantum mechanical limit, not a technological limit, to the dimensioning of a gate.
Am I wrong?
going down to single nanometer is possible and even sub nanometer but that is now atoms thick which is where the issues lie. 5nm requires a lot of technology advancements to reach.

I forget the maximum limit but it was like .1 to .5nm or something because that is where it is like only a few atoms thick.

https://en.wikipedia.org/wiki/5_nanometer
Posted on Reply
#6
Boosnie
HopelesslyFaithful
going down to single nanometer is possible and even sub nanometer but that is now atoms thick which is where the issues lie. 5nm requires a lot of technology advancements to reach.

I forget the maximum limit but it was like .1 to .5nm or something because that is where it is like only a few atoms thick.

https://en.wikipedia.org/wiki/5_nanometer
Thanks
BTW I found an old video that explains the situation (I was remembering the content of the vid wrong, hence my initial question)

Posted on Reply