Tuesday, November 5th 2019
Intel CFO Talks About 7nm Rollout, Delay in 10nm, Increased Competition from AMD
Intel CFO George Davis in an interview with Barron's commented on the company's financial health, and some of the reasons behind its rather conservative gross margin guidance looking forward to at least 2023. Intel's current product stack is moving on to the company's 10 nm silicon fabrication process in a phased manner. The company is allocating 10 nm to mobile processors and enterprise processors, while brazening it out with 14 nm on the client-desktop and HEDT platforms until they can build 10 nm desktop parts. AMD has deployed its high-IPC "Zen 2" microarchitecture on TSMC's 7 nm DUV process, with plans to go EUV in the coming months.
"We're still keenly focused on gross margin. Everything from capital efficiency to the way we're designing our products. What we've said though, the delay in 10 nanometer means that we're going to be a little bit disadvantaged on unit cost for a period of time. We actually gave guidance for gross margin out in 2021 to help people understand. 2023 is the period that we were ultimately guiding [when] we're going to see very strong revenue growth and margin expansion. We've got to get through this period where we have the 10 nanometer being a little bit late [as] we're not optimized on a node that we're on. But [by] then we're moving to a two to two and a half year cadence on the next nodes. So we're pulling in the spending on 7 nanometer, which will start up in the second half of 2021 because we think it's the right thing to do competitively," he said.
Davis and Barron's also spoke about Intel's 7 nm rollout plans. Davis stated that Intel's 7 nm silicon fabrication node is expected to begin mass-production of chips only by the second half of 2021. Barron's then turned the discussion to AMD and the traction its EPYC "Rome" server processors are gaining with enterprises. "We said we expect to have heightened competition over the next 18 to 24 months. And our outlook reflects that. Our view on the nature of that competition and impact hasn't really changed since we gave [our] longer term forecast in May," he said. You can read the full Barron's interview from the source link.
Source:
Barron's
"We're still keenly focused on gross margin. Everything from capital efficiency to the way we're designing our products. What we've said though, the delay in 10 nanometer means that we're going to be a little bit disadvantaged on unit cost for a period of time. We actually gave guidance for gross margin out in 2021 to help people understand. 2023 is the period that we were ultimately guiding [when] we're going to see very strong revenue growth and margin expansion. We've got to get through this period where we have the 10 nanometer being a little bit late [as] we're not optimized on a node that we're on. But [by] then we're moving to a two to two and a half year cadence on the next nodes. So we're pulling in the spending on 7 nanometer, which will start up in the second half of 2021 because we think it's the right thing to do competitively," he said.
50 Comments on Intel CFO Talks About 7nm Rollout, Delay in 10nm, Increased Competition from AMD
For example if you look up 7nm in Wikipedia under the "7 nm Process nodes and process offering section. en.wikipedia.org/wiki/7_nanometer. You see Intel 10nm more dense then all the other companies none euv 7nm but the 7nm base on euv are more dense then intel 10nm. One of the mistakes Intel made was being way to aggressive in there 10nm process. They way trying to hit a density level 4 years ago that no other company even attempted until EUV was available and obviously in hind site was a massive failure for intel.
""If Intel’s 7-nanometer node ramps as planned in 2021, we estimate it at around 237.18 MTr/mm², ""
Intel may decide to go with less dense 7nm, but who knows. 10nm is history now. Only suitable for chipsets in the not so distant future.
Of course 14nm is around 44 Mt/mm2. Does it mean die area will suddenly shrink to 20%, probably not.
We will never see 10nm in decent numbers, what would be the point, so the jump is made 14 to 7nm and ratio of compaction 4-5 times.
That was my only point. If I had to bet, I would bet you are right. But I don't present bets as fact.Some of the prototyped 10nm dies are defintely not "small server" material.
The problem appears with the space between transistors. That is why you have EUV, DUV etc. techniques to connect the transistor together which is always a problem.
The 5nm and even 3nm transistors are here already but the manufacturing process to (semiconductor device fabrication) is not ready yet. Although the 5nm TSMC is ready I guess but it is not in production yet.
en.wikipedia.org/wiki/7_nanometer#7_nm_process_nodes_and_process_offerings
Some of the parameters listed in the table - Transistor Gate Pitch, Transistor Fin Pitch, Transistor Fin Height, Minimum (Metal) Pitch are all parameters for physical size for various aspects of transistor components. Notably, these are all far bigger than 7nm.
Historically, the nm number in process name was gate length, then after some processes having just scaled numbered names half-pitch of memory cell was used and this again kind of goes out the window with FinFET at 14nm and smaller. Feature size (for couple/several different features) or resolution are the best generic descriptions of what the node number is about but even that is not accurate or true at this stage.
ice lake is architecture on 10+, tiger is optimisation of ice lake on 10++, then again sapphire rapids would be a process 7+, so what other tocs are there other than tiger.
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