Thursday, June 11th 2020

Intel "Rocket Lake-S" a Multi-Chip Module of 14nm Core and 10nm Uncore Dies?

VLSI engineer and industry analyst, @chiakokhua, who goes by "Retired Engineer" on Twitter, was among the very first voices that spoke about 3rd gen Ryzen socket AM4 processors being multi-chip modules of core- and uncore dies built on different silicon fabrication processes, which was an unbelievable theory at the time. He now has a fantastic theory of what "Rocket Lake-S" could look like, dating back to November 2019, which is now re-surfacing on tech communities. Apparently, Intel is designing these socket LGA1200 processors to be multi-chip modules, similar to "Matisse" in some ways, but different in others.

Apparently, "Rocket Lake-S" is a multi-chip module of a 14 nm die that holds the CPU cores; and 10 nm die that holds the uncore components. AMD "Matisse" and "Vermeer" too have such a division of labor, but the CPU cores are located on dies with a more advanced silicon fabrication process (7 nm), than the die with the uncore components (12 nm).
The 14 nm CPU die on "Rocket Lake-S" holds "Willow Cove" CPU cores that are purported to introduce significant IPC gains over "Skylake." In this die, there are CPU cores and a reduced-functionality system agent, which are bound together by a Ring-bus interconnect. This system agent talks to its counterpart on the uncore die (aka "GPU die"), over EMIB interconnect.

The 10 nm GPU die (aka uncore die) features the processor's Gen12 Xe iGPU with up to 96 execution units, a dual-channel DDR4 memory controller, and a PCI-Express 4.0 root-complex, besides other minor components related to the iGPU, such as its display- and media engines.

Unlike every past Intel mainstream desktop generation since "Lynnfield," the "Rocket Lake-S" MCM puts out a total of 24 PCI-Express lanes. 16 of these are assigned as PEG (PCI-Express Graphics, or the main PCI-Express x16 slot on the platform); and 8 lanes are assigned as chipset bus. In past microarchitectures, including "Comet Lake-S," the processor only put out 20 lanes, 16 of which are toward PEG, and 4 toward the chipset-bus (DMI).

This won't be the first time that Intel took the MCM approach in its mainstream desktop processors. The first generation "Clarkdale" desktop processor in the LGA1156 package was an MCM of a 32 nm CPU die, and a 45 nm uncore die (which contained the iGPU).

Why Intel chose to give the iGPU, rather than the CPU cores, the advantage of the more advanced silicon fabrication process is a mystery that will only be solved after launch. Perhaps it's simply not possible to build a Gen12 iGPU on 14 nm, while the efficiency of "Willow Cove" CPU cores, originally designed for 10 nm+, can survive a back-port to 14 nm better. "Willow Cove" cores make their debut with the "Tiger Lake-U" mobile processors.
Source: Chiakokhua (Twitter)
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23 Comments on Intel "Rocket Lake-S" a Multi-Chip Module of 14nm Core and 10nm Uncore Dies?

#1
ShurikN
:sniff: :sniff:
Is that glue I'm smelling?!
Posted on Reply
#4
ncrs
btarunr
Pentium Pro was HEDT :)
From Wikipedia:
[...]was originally intended to replace the original Pentium in a full range of applications[...]
Debatable ;)
Posted on Reply
#5
londiste
Wouldn't it make much more sense the other way around - 10nm cores and 14nm everything else? Both Intel and AMD have said at various points that IO does not scale down too well. IO Die and the "GPU Die" on this picture both have a bunch of IO at its core. I really don't see what 10nm uncore would bring to the table. They are hopefully not going that big with the GPU.
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#6
ncrs
londiste
Wouldn't it make much more sense the other way around - 10nm cores and 14nm everything else?
I really don't see what 10nm uncore would bring to the table. They are hopefully not going that big with the GPU.
Intel has started Gen12 design with 10nm in mind. Porting this over to 14nm would cost a lot of money. It's probably the same with PCIe 4.0 controllers and other I/O.

10nm/+ is (currently) unable to attain as high clocks as 14nm+++++++.
Posted on Reply
#7
jeremyshaw
ncrs
Intel has started Gen12 design with 10nm in mind. Porting this over to 14nm would cost a lot of money. It's probably the same with PCIe 4.0 controllers and other I/O.

10nm/+ is (currently) unable to attain as high clocks as 14nm+++++++.
Yeah, that's my guess as well. Intel probably also designed their PCIe 4 IP (or licensed) for 10nm, not 14nm, along with their newer RAM controllers and display controllers. Meanwhile, the CPU teams have been getting a LOT of experience on 14nm, while all of the other teams have been waiting on the few meager 10nm products.
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#8
HugsNotDrugs
Die costs increase dramatically as monolithic dies become larger. Packing in several cores, a large capable GPU and advanced I/O quickly gets out of hand. Splitting these between multiple dies on a single package drives costs way down. It also distributes heat a bit better.

Intel was caught with their pants down because they were reliant on small monolithic dies where they could fit four cores and a GPU while keeping costs low. That doesn't scale up well to meet the competition AMD is bringing, which is brilliant.

It's great to see Intel gluing chips together.
Posted on Reply
#9
R0H1T
btarunr
The 14 nm CPU die on "Rocket Lake-S" holds up to eight "Willow Cove" CPU cores that are purported to introduce significant IPC gains over "Skylake."
I can count 10 cores in the image above, also WTH is up with that ginormous IGP :wtf:

Posted on Reply
#10
ncrs
R0H1T
WTH is up with that ginormous IGP :wtf:
The Rocket Lake diagram might not be to scale, but the iGPU in Ice Lake is relatively big as well:



Edit: oh and Tiger Lake is supposed to have 1.5x the EU of Ice Lake for the GPU which will also be Gen12. How will that affect the size? Only Intel knows ;)
Posted on Reply
#11
Assimilator
btarunr
Apparently, Intel is designing these socket LGA1200 processors to be multi-chip modules, similar to "Matisse" in some ways, but different in others. Apparently, "Rocket Lake-S" is a multi-chip module of a 14 nm die that holds the CPU cores; and 10 nm die that holds the uncore components
Better to use "Allegedly" or "According to "Retired Engineer"".
Posted on Reply
#12
yeeeeman
If true, should be interesting.
Posted on Reply
#13
ppn
R0H1T
I can count 10 cores in the image above, also WTH is up with that ginormous IGP :wtf:
The 10nm part of RKL should be ~~92mm2, plus the additional 24 PCIe lanes.
The CPU portion 4C 41mm2 is removed and then upscaled to 14 nm and 128mm2 8C.

So the CPU is bigger in the end, and the GPU part isn't very likely to have 96ALu like in TGL but 24 instead.
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#14
Valantar
If this turns out to be true, it's just another illustration of how horribly broken Intel's 10nm process still is. Better suited for an I/O die than for high-performance compute cores, even though I/O by its very nature is the thing that scales the worst with node shrinks, and has the least to gain from it? Yeah, that process node is crap.
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#15
Kaotik
nevermind this, they're both wrong (the handdrawn and the old diagram from last november which is used in this news piece)
Posted on Reply
#16
ppn
Well if that is the case, who would want that abomination with the memory controller being on a separate die.. Intel went back in time to I5-650. Just double the core count of the already decent Tigerlake increase the size from 146 to 190mm2, that is all it takes, and at least 28 pcie lanes for 1x4 NVMe to CPU + 2x4 to the PCH + 16x GFX.. Now we have to wait for the refresh Sandybridge-like. to put everything back together.
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#17
CrAsHnBuRnXp
Can intel just eff off with iGPU's already? We dont want them.
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#18
ppn
The GPU part takes the space that can be occupied by 4 perfect Willow Coves. This is so frustrating at times. Just offer the 2 options you either want 8 cores or 4 cores+GPU,. same size same price.

Posted on Reply
#19
dont whant to set it"'
"Cheryl /( Carol / Corina / various other names she went by ) : can I glue up?"
To which Malory responded :"It's your house."
Posted on Reply
#20
1d10t
Now we just wait for "Intel 10nm are better than TSMC 7nm / 5nm bla..bla "
Posted on Reply
#21
birdie
Why Intel chose to give the iGPU, rather than the CPU cores, the advantage of the more advanced silicon fabrication process is a mystery that will only be solved after launch.
No mistery here: iGPU runs at a much lower frequency (4-5 time slower than CPU cores) and Intel's 10nm node works just fine for this use case.
Posted on Reply
#22
Assimilator
birdie
No mistery here: iGPU runs at a much lower frequency (4-5 time slower than CPU cores) and Intel's 10nm node works just fine for this use case.
Yup, IGP frequency on Skylake is 1.15GHz max. On Lakefield it's a mere 500MHz, although whether that's an artifact of 10nm being terrible or that chip's focus on low power vs performance (or both) is yet to be seen.
Posted on Reply
#23
londiste
Assimilator
Yup, IGP frequency on Skylake is 1.15GHz max. On Lakefield it's a mere 500MHz, although whether that's an artifact of 10nm being terrible or that chip's focus on low power vs performance (or both) is yet to be seen.
7W is a pretty heavy restriction.
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