Friday, July 3rd 2026
Intel Readies Two 22-Core "Nova Lake-S" SKUs with 108 MB bLLC Cache for Gaming
According to well-known Intel leaker Jaykihn, Intel is preparing two "Nova Lake-S" CPU models with a 22-core configuration, enhanced by the big Last Level Cache (bLLC). These processors are part of the Core Ultra 5 400S family, and Intel is developing two mid-range configurations, each with 22 cores. Both models will feature 6 "Coyote Cove" P-Cores, 12 "Arctic Wolf" E-Cores, and 4 LPE-Cores. This design includes a single compute die aimed at mid-range gaming rigs. Alongside the 22 cores, Intel plans to add an extra 108 MB of bLLC cache to boost gaming performance, similar to AMD's approach with its Ryzen X3D gaming CPUs, which currently lead in gaming performance. Intel aims to match raw CPU compute power with newer CPU cores and use bLLC to improve latency-sensitive tasks like gaming. The only difference between the two new models is that one is an unlocked 125 W TDP version, part of the "K" overclockable family, while the other is a 65 W base TDP model.
Recently, it has been observed that Intel's upcoming Z9x0 platform for "Nova Lake-S" will support up to 52 cores in a single LGA-1954 socket. Some early rumors suggest a PL2 power draw of 474 W, which is a significant increase over previous designs. This is understandable, considering that the design brings workstation-like core counts into the consumer sector for the first time. Regarding the socket, Intel's LGA-1954 has been pictured with a 2-lever independent loading mechanism (ILM), similar to what Intel's HEDT sector uses. This is typically reserved for larger CPU packages, and with the pin count now nearing 2,000 socket pins, it is a necessary choice for Intel. Importantly, the first "Nova Lake-S" CPU SKUs are scheduled for release in just a few months, likely leading to more rumors as we approach the final launch.
Source:
Jaykihn on X
Recently, it has been observed that Intel's upcoming Z9x0 platform for "Nova Lake-S" will support up to 52 cores in a single LGA-1954 socket. Some early rumors suggest a PL2 power draw of 474 W, which is a significant increase over previous designs. This is understandable, considering that the design brings workstation-like core counts into the consumer sector for the first time. Regarding the socket, Intel's LGA-1954 has been pictured with a 2-lever independent loading mechanism (ILM), similar to what Intel's HEDT sector uses. This is typically reserved for larger CPU packages, and with the pin count now nearing 2,000 socket pins, it is a necessary choice for Intel. Importantly, the first "Nova Lake-S" CPU SKUs are scheduled for release in just a few months, likely leading to more rumors as we approach the final launch.

279 Comments on Intel Readies Two 22-Core "Nova Lake-S" SKUs with 108 MB bLLC Cache for Gaming
In other words, it is better than the cpu uarchs used by everyone here right now.18 out of 22 cores, each core is much better than the best core you are using right now
lp-e,npu,igpu,etc6p+12e will provide 18 high-quality threads for the OS, while zen6 can only provide 12, with the rest being low-quality smt, thereby affecting performance. For ue6, intel 24core is the most advantageous, while zen6 12c24t and novalake 18c18t should perform closely in scheduling. p core is not the critical factor, and Arctic Wolf e core performance should reach over 90% of p core.The main difference lies in the n3b node yield, dtco, which allows intel to offer a cheaper 285k.
i don't intend to upgrade again for a solid 5-10 years, so i don't care if this is one gen mobo. either way, I will be keeping my old mobo/7800x3d as backup rig.
Gracemont e cores were compared to 10th gen p cores almost FIVE years ago. Skymont e cores have 30% higher IPC and 20% faster clocks speeds than Gracemont, which means they are comparable to 12th gen p cores. There is even a generous reddit user who went through the trouble of proving this.
overclocking/comments/1p2vaif/sharing_a_foolish_test_i_did_all_cores_vs_ecores
17% performance drop for e-cores-only means that only 12 Skymont e cores are faster than an entire 12700k.
Also there were some rumours long ago about L2 sharing in P cores (4MB per two cores)... has this been confirmed?Quite believable in ST testing. MT is more unpredictable, especially if P cores will be clustered too.
Intel is really getting itself ready for the unified core quite soon, and that one will be a descendant of the more modern E core, not the P core, whose architecture has been exploited in full by now.
Approximations for "IPC" these days mostly consist of various batch loads, which aren't latency sensitive or logically complex, which means two CPUs with similar scores may have very different performance characteristics in real world usage. What's made Intel's CPUs for generations more responsive is a very effective front-end, even back with Coffee Lake/Comet Lake vs. Zen 3; Intel's were more snappy while AMD's were better for larger batch loads, but in most synthetics the latter looked much better. And the more CPU makers are focusing on looking good on paper, the less useful single metrics are for gauging performance.
But if we have all these cores, pcores for their single threaded performance, ecores for multithreaded die area efficiency, low power cores for background tasks or something?.... multiple large caches.... Well, its like there's no compromises here... Well except maybe lack of hyperthreading, if you consider that an advantage. So, I hope they are affordable for normal humans. High prices I expect, I just hope its not ram all over again.
Maybe thats why they are preparing some of the midrange chips first. Don't want people to see the price of the flagship yet.... maybe even the midrange will be hard to swallow.
So... the question is, do I buy the 270k PLUS while I still can?
Raptor Lake
Raptor Lake refresh
Bartlet Lake
Raptor Lake Next
How did I manage to miss some?12100
13100
14100
They even look like the same piece of silicon with updated info on package.Do they need it?
✅ ... CPU socket
✅ ... PCIe Gen 5 x16 slot (used or not)
✅ ... PCIe Gen 5 x4 slot
Covers 95% of use cases.
In the right size you may put it into shoe box and call it a day.
The Darkmont E-Cores in Nova Lake have instruction parity with the P-Cores and on top of that are decently improved over the previous Skymont E-Cores in both PPC and higher clock speeds.
Expensive to upgrade? I think that the RAM sticks and SSDs are reusable.
I believe that Intel may want to regain more market share and better image in consumer PCs and they may go on in an agressive great value for money strategy defined by 250K and 270K. So at least some of these new CPUs could be a good value for money and the only remaining piece of the puzzle is the cost of the motherbords.
Looking at AMD CPUs comparing 9600X to 9700X or further to a 9950X is the wrong way because frequency isn't constant for the same core/thread count.
tpucdn.com/review/amd-ryzen-5-9600x/images/boost-clock-analysis.png
tpucdn.com/review/amd-ryzen-7-9700x/images/boost-clock-analysis.png
tpucdn.com/review/amd-ryzen-9-9950x/images/boost-clock-analysis.png
Beyond that there is SMT which could skew the result, when it comes to thread count even the 9600X has enough threads for games, so if the game engine would properly take advantage of these threads you can't really get obvious scaling (due to only the cores) from 9600X to 9950X because the 9600X has enough virtual threads to compensate for the lack of physical cores. So those would have to be exhausted before a hard cut off in the performance is observed.
Thus the right approach would be to use a homogeneous CPU and disable cores. That way the cache and frequency are constant (well ignoring the boosting algorithm anyway).
Right now the 270K/285K could be used for Intel with P-only config and use 4, 6 and 8 cores.
For AMD either 9700X or 9800X3D with SMT off and using 4, 6 and 8 cores.
Only in this manner we can reliably identify the games that can genuinely use many cores.
The Zen6 "10800X3D" will be an even better candidate due to its 12 core CCD, it will have more than enough homogeneous physical cores to cover outliers.In the review the older Arrow Lake SKUs are using 200S Boost enabled so there's no disadvantage there.
It's something alright, I don't know/think if it's the BOT or something else but it's working because from what I've seen comparing the 285K vs 270K at the same core clocks (P and E), same NGU, D2D, Ring whatever yields worse results in CB multi. In single thread the 285K still has an advantage due to the Thermal Velocity Boost algorithm.I'm counting on it.Will you be satisfied by its performance for your use case?
If yes do it, if not then get ready for single full tile with bLLC NL at $600.
If so then the only chance for a significant discount is if it's beaten by the Zen6 "10800X3D" in games.
Also keep in mind that NL might need higher speed RAM (compared to the 270K) to achieve its full potential. This is a minor drawback but since you'd be willing to wait then every aspect counts.AMD is doing the same.
I agree it's a major inconvenient.
250 W MTP with the current clocks is stupid for the 265K, 200 max should have been the target.
The 9700X is power constrained at 65/80 W it should've had 80/110 W something like that with slightly higher clocks.
I doubt Intel would change its strategy although I would bet that is the winning approach for next gen.
Suppose AMD is stupid and puts higher clocks on the "10950X3D" compared to the "10800X3D".
tpucdn.com/review/amd-ryzen-7-9800x3d/images/boost-clock-analysis.png
tpucdn.com/review/amd-ryzen-7-9850x3d/images/boost-clock-analysis.png
tpucdn.com/review/amd-ryzen-9-9950x3d/images/boost-clock-analysis.png
That means if Intel does the opposite, the single full tile with bLLC can win in games vs the "10800X3D", whereas the NL dual tile flagship will lose in games against the "10950X3D" but still win in MT, which is well the point of that CPU. I mean buying that primarily for gaming is definitely a "choice".The compute tile is made by TSMC just like with Arrow Lake.
Jaykihn mentioned it, credibility is quite high.
I think p core was more dragged down by lioncove's crappy issues and slow R&D progress. Lioncove directly ruined a generation of DC, replaced by redwoodcove x, DMR is still very late and smt was canceled, while griffincove's performance might be very good. But the e core team can stably bring quite decent IPC every 2 years, and the area is much smaller. What more can the next gen of p core do, maybe another lioncove, delays, cancellations, the risk is too high.I agree that using SPEC to measure cpu uarch is outdated, but I don't know a better way to measure it. The e core uarch is also a general-purpose cpu works for any task.
in SPEC2017 fp 519, the performance of the e core is clearly inferior to the p core, else is fine.
I was wrong about the latency; skymont has a higher latency than p core when it is below 3000kb. even if this is the case, it is nothing to be happy about that the p core, which occupies more area, performs similarly in SPEC IPC to the e core, which occupies less area.
the p core needs to be more well-rounded. But where the e core underperforms, it is a trade-off made for area/efficiency, I can understand it. since the e core is part of a hybrid design, the real world scenario might be that such tasks are allocated to the p core.
Perhaps it is an advantage in hybrid designs and low-power devices. Intel might improve unified p core L1/L2 to low latency and high bandwidth, but retain this part in unified e core.
And I highly doubt these 2 particular CPUs will be cheap in the slightest with that big cache pool. They will be halo tier, meaning as expensive as the current X3D chips, probably more so if they do indeed outperform them. Wouldn't be surprised to see the $999 tier make a comeback since the 9950X3D2 is sitting at $900.