Friday, February 20th 2026
Intel "Nova Lake-S" Coming in 2027, CES Launch Alongside AMD "Olympic Ridge" Likely
It was revealed in a recent leak that the next-gen AMD Zen 6 Ryzen CPUs would be delayed until 2027, and it has now emerged, that the upcoming Intel "Nova Lake-S" Core Ultra Series 4 CPUs may be joining AMD for an early 2027 launch, when previous reports placed the launch in late 2026. The news comes by way of ubiquitous leakers, HXL on X and Golden Pig Upgrade on Weibo, who say that a CES 2027 launch seems likely for both new CPU generations.
Previously, we got a taste of what to expect from Nova Lake-S in a series of leaks and rumors, which pointed to increased NPU performance as well as core counts that range from 12 on the low-end (4 P-cores, 4 E-cores, 4 LP-cores) to 52 on the high-end (16 P-cores, 32 E-cores, 4 LP-cores). Obviously, these are early leaks, and the official launch is still a way out, so dates may still change, but it seems as though the current silicon and DRAM shortages may result in the lengthening of product launch cycles across the PC industry in general—an outcome that was previously predicted.
Sources:
Weibo, HXL on X
Previously, we got a taste of what to expect from Nova Lake-S in a series of leaks and rumors, which pointed to increased NPU performance as well as core counts that range from 12 on the low-end (4 P-cores, 4 E-cores, 4 LP-cores) to 52 on the high-end (16 P-cores, 32 E-cores, 4 LP-cores). Obviously, these are early leaks, and the official launch is still a way out, so dates may still change, but it seems as though the current silicon and DRAM shortages may result in the lengthening of product launch cycles across the PC industry in general—an outcome that was previously predicted.
118 Comments on Intel "Nova Lake-S" Coming in 2027, CES Launch Alongside AMD "Olympic Ridge" Likely
If AMD's Zen 6 isn't really fast, an upgraded E core from Intel could be seen as "as fast" or "fast enough" compared with Zen 6's cores, so people will be much more acceptable in the idea of buying such a configuration, an
E coresUnified cores only configuration. We know from the era of the first Zen series, that more cores win market share, if they are fast enough and more than what the competition offers. Of course in the first Zen series era, going from 4 to 8 cores did made sense, going from let's say, 40 to 64, I don't know if it does. Performance per core and in some applications in general that needs no more than single digit cores, but as fast as possible, like 99% of apps, could take a step back compared to the performance offered by Nova Lake's P cores, but fast E cores are offering Intel the chance to completely abandon big cores and probably that's where they are going. With GPUs doing the heavy lifting in most of current server applications and probably future desktop applications also, while NPUs taking over much of the trivial AI stuff, Intel could go that route for everything, even for Xeons. More so, in the server market their Xeon designs could align more with Nvidia's approach with Grace CPUs, where plenty of small cores are probably just managing and feeding with data the big number of GPUs.Unified Core did indeed defeat Griffin Cove, the last p-core architecture, but It does not mean Intel is giving up on hybrid.
Also the FPUs are not appealing.
As for the FPUs, they could go with a similar design to what AMD has done: dual pump 256-bit paths for dense offerings, full 512-bit paths for high performance offerings.
I think it's pretty reasonable to assume that they'd increase the FP's register file and scheduling queues to accommodate for the wider instructions.
Bringing back SMT in their current implementation would make little sense for most markets, it adds lots of pipeline complexity, security implications and competition for cache and front-end resources for increasingly diminishing returns. With APX coming with Nova Lake, recompiled software will have far less pipeline stalls than before, resulting in even less gains for their SMT implementation. For it to make any sense, they would have to take a different approach, or somewhere down the line make an architecture with resource shared between cores in a better way than Bulldozer (and there have been rumors of such), and they are probably designing many experimental CPU designs.
But either way, SMT is a dead end. I believe SMT should have ended with quad cores, as these design constraints have held back the advancement of CPU architectures ever since.
With APX, it would make sense to scale high performance designs to e.g. 8 integer pipelines and 4 FMA sets or more, perhaps even larger vector sizes and cache lines, this combined with power gating would make much more sense for the foreseeable future. There are a lot of possibilities with tiles and stacking to make very powerful cores.Cinebench is a specific benchmark of one niche load, specifically Cinema 4D's 3D rendering, it should never be used by itself to estimate generic performance, and absolutely not to estimate "IPC".