Thursday, September 10th 2020

Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications

Rambus Inc. (NASDAQ: RMBS), a premier silicon IP and chip provider making data faster and safer, today announced it has achieved a record 4 Gbps performance with the Rambus HBM2E memory interface solution consisting of a fully-integrated PHY and controller. Paired with the industry's fastest HBM2E DRAM from SK hynix operating at 3.6 Gbps, the solution can deliver 460 GB/s of bandwidth from a single HBM2E device. This performance meets the terabyte-scale bandwidth needs of accelerators targeting the most demanding AI/ML training and high-performance computing (HPC) applications.

"With this achievement by Rambus, designers of AI and HPC systems can now implement systems using the world's fastest HBM2E DRAM running at 3.6 Gbps from SK hynix," said Uksong Kang, vice president of product planning at SK hynix. "In July, we announced full-scale mass-production of HBM2E for state-of-the-art computing applications demanding the highest bandwidth available."
The fully-integrated, production-ready Rambus HBM2E memory subsystem runs at 4 Gbps without PHY voltage overdrive. Rambus teamed with SK hynix and Alchip to implement the HBM2E 2.5D system to validate in silicon the Rambus HBM2E PHY and Memory Controller IP using TSMC's N7 process and CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging technologies. Co-designing with the engineering team from Rambus, Alchip led the interposer and package substrate design.

"This advancement of Rambus and its partners, using TSMC's advanced process and packaging technologies, is another important achievement of our ongoing collaboration with Rambus," said Suk Lee, senior director of the Design Infrastructure Management Division at TSMC. "We look forward to a continued partnership with Rambus to enable the highest performance in AI/ML and HPC applications."

"Alchip brought a demonstrated track record of success in 7nm and 2.5D package design to this initiative," said Johnny Shen, CEO of Alchip Technologies. "We're extremely proud of our contributions to Rambus' breakthrough achievement."

Rambus has 30 years of high-speed memory design applied to the most demanding computing applications. Its renowned signal integrity expertise was key to achieving an HBM2E memory interface capable of 4 Gbps operation. This raises a new benchmark for meeting the insatiable bandwidth requirements of AI/ML training.

"With silicon operation up to 4 Gbps, designers can future-proof their HBM2E implementations and can be confident of ample margin for 3.6 Gbps designs," said Matthew Jones, senior director and general manager of IP cores at Rambus. "As part of every customer engagement, Rambus provides reference designs for the 2.5D package and interposer to ensure first-time right implementations for mission-critical AI/ML designs."

Benefits of the Rambus HBM2E Memory Interface (PHY and Controller):
  • Achieves the industry's highest speed of 4 Gbps per pin, delivering a system bandwidth of 460 GB from a single 3.6 Gbps HBM2E DRAM 3D device.
  • Fully-integrated and verified HBM2E PHY and Controller reduces ASIC design complexity and speeds time to market
  • Includes 2.5D package and interposer reference design as part of IP license
  • Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
  • Features LabStation development environment that enables quick system bring-up, characterization and debug
  • Supports high-performance applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems
For more information on the Rambus Interface IP, including our PHYs and Controllers, please visit rambus.com/interface-ip.
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17 Comments on Rambus Advances HBM2E Performance to 4.0 Gbps for AI/ML Training Applications

#3
AnarchoPrimitiv
By 460GBps form a "single device", do they mean a single HBM2e stack? If so, does that mean near 2TB/s for four stacks?
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#4
Dredi
AnarchoPrimitiv
By 460GBps form a "single device", do they mean a single HBM2e stack? If so, does that mean near 2TB/s for four stacks?
Yes.
Posted on Reply
#5
Apocalypsee
Are they going to patent troll this one as well?
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#6
xkm1948
I hope Navi2X uses this instead of GDDR6
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#7
Tomorrow
xkm1948
I hope Navi2X uses this instead of GDDR6
Little chanche of that. Navi will use G6 for cost reasons.
Posted on Reply
#9
Patriot
Apocalypsee
Are they going to patent troll this one as well?
Darksword
DIAF Rambus.
First thing I think of when I hear Rambus, Maker of failed past products and patent troll.
Posted on Reply
#10
mtcn77
Apocalypsee
Are they going to patent troll this one as well?
They need the feasibility for rapid deployment. There is only 1 advantage 2.5D has over 3D and that is seamless correction after manufacture. They can machine test it, if things are known to work.
Posted on Reply
#11
AnarchoPrimitiv
Dredi
Yes.
I soooooo want AMD to make an APU with 24-36 CUs and a 4-8GB HBM2e stack integrated into it that can dynamically switch between VRAM and L4 cache depending on need. I'm constantly looking at AMD patents and they do have the IP for such a product.

On another note, they also have recent patents for MCM GPUs that utilize a technique called "GPU masking" to make multiple GPU chiplets appear as a single logical device to both the OS and Graphics API, so I can't wait to see that come out in a few years

Posted on Reply
#12
sergionography
AnarchoPrimitiv
I soooooo want AMD to make an APU with 24-36 CUs and a 4-8GB HBM2e stack integrated into it that can dynamically switch between VRAM and L4 cache depending on need. I'm constantly looking at AMD patents and they do have the IP for such a product.

On another note, they also have recent patents for MCM GPUs that utilize a technique called "GPU masking" to make multiple GPU chiplets appear as a single logical device to both the OS and Graphics API, so I can't wait to see that come out in a few years


It is my understanding that next gen will be multi chip/chiplet based for both AMD and Nvidia.
Posted on Reply
#13
Imsochobo
Tomorrow
Little chanche of that. Navi will use G6 for cost reasons.
G6X or hbm, I don't see how it could be that different in cost tbh.
also biggest navi 6900XT could have HBM easily!
Posted on Reply
#14
Tomorrow
Imsochobo
G6X or hbm, I don't see how it could be that different in cost tbh.
also biggest navi 6900XT could have HBM easily!
G6X is Nvidia exclusive. Just like G5X was. HBM will not come to consumer cards anytime soon.
Posted on Reply
#15
R0H1T
I don't think it's exclusive, AMD et al were going to move to GDDR6 & HBME that's why GDDR5x was largely ignored & Micron took quite a hit for that IIRC.
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#16
Imsochobo
Tomorrow
G6X is Nvidia exclusive. Just like G5X was. HBM will not come to consumer cards anytime soon.
hbm have been on consumer cards for 5 years ?
Posted on Reply
#17
Tomorrow
Imsochobo
hbm have been on consumer cards for 5 years ?
I meant new cards. Technically the last "consumer" card was Radeon VII that used HBM. Even that was just rebranded workstation card. I would consider Vega and Fiji the only true consumer cards that used HBM.

And with G6X largely equaling HBM2 in terms of bandwith (Radeon VII and 3090 are both roughly 1TB/s) i see even less reason for HBM.
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