News for "32nm"

Intel Corporation today reported third-quarter revenue of $9.4 billion. The company reported operating income of $2.6 billion, net income of $1.9 billion and earnings per share (EPS) of 33 cents.

"Intel's strong third-quarter results underscore that computing is essential to people's lives, proving the importance of technology innovation in leading an economic recovery," said Paul Otellini, Intel president and CEO. "This momentum in the current economic climate, plus our product leadership, gives us confidence about our business prospects going forward. As we look ahead, Intel's game-changing 32nm process technology will usher in another wave of innovation from new, powerful Intel Xeon server platforms to high-performance Intel Core processors to low-power Intel Atom processors."

Highlights include:

• Third-Quarter Revenue $9.4 Billion, Strongest Second-to-Third-Quarter Growth in over 30 years
• Gross Margin 58 Percent, Up 7 Points Sequentially
• Operating Income $2.6 Billion
• Net Income $1.9 Billion
• EPS 33 Cents

To read the complete earnings release, visit this page.

As the semiconductor industry begins its transition to the next technology node, GLOBALFOUNDRIES is on track to take its position as the foundry technology leader. On October 1 at the Global Semiconductor Alliance Emerging Opportunities Expo & Conference in Santa Clara, Calif., GLOBALFOUNDRIES (Booth 321) will provide the latest details on its technology roadmap for the 32nm/28nm generations and its innovative "Gate First" approach to building transistors based on High-K Metal Gate (HKMG) technology.

"With each new technology generation, semiconductor foundries are increasingly challenged with the economics to sustain R&D and the know-how to bring these technologies to market in high-volume," said Len Jelinek, director and chief analyst, iSuppli. "With a heritage of rapidly ramping leading-edge technologies to high volumes at mature yields, combined with aggressive investments in capacity and technology, GLOBALFOUNDRIES is uniquely-positioned to challenge for next-generation foundry leadership."

Toshiba America Electronic Components, Inc. (TAEC), a U.S. marketing arm of Toshiba Corporation for electronic components, today announced a series of solid state drive (SSD) modules using the latest generation Toshiba 32nm MLC NAND flash, at Intel Developers Forum 2009. The Toshiba SG2 modules are offered in two types, one based on the new low-profile mini-SATA (mSATA) interface standard and the other a Half-Slim type, which uses a SATA connector. The drives are available in 30GB1 and 62GB modules. Volume production will start in October.

The two types of modules, each smaller than a business card, provide greater design flexibility and save space and cost compared to SSDs with hard disk drive form factors and cases. The 62GB module is only one seventh the volume and one eighth the weight of a 2.5-inch form factor SSD, and consumes half the power. With interface speeds up to 3 gigabits per second (Gb/s), a maximum sequential read speed of 180 megabytes per second (MBps)3,4 and a maximum sequential write speed of 70MBps,3,4 the modules will help bring the performance advantages of SSDs to notebooks, portable electronics and embedded systems. An advanced controller features a translation mode, which enables any drive configuration, and the drive supports 28-bit LBA (Logical Block Address) mode commands and 48-bit LBA mode commands. Multi-word DMA, Ultra-DMA modes and Advanced PIO commands are supported. The drives have an optional capability for secure Full Disk Encryption (FDE) backup that prevents unauthorized data access.

Intel President and CEO Paul Otellini today announced the company would spend $7 billion over the next two years to build advanced manufacturing facilities in the United States. The investment funds deployment of Intel's industry-leading 32 nanometer (nm) manufacturing technology that will be used to build faster, smaller chips that consume less energy. The commitment represents Intel's largest-ever investment for a new manufacturing process.

On the course of coming up with mainstream derivatives of the Nehalem architecture, for Intel, there seems to be a big deal of uncertainty surrounding the dual-core parts. Havendale (desktop) and Auburndale (notebook) were stated by initial company road-maps as the company's dual-core chips. Later, news emerged of Intel reportedly scrapping both chips to find a 32 nm replacement in another chip codenamed Arrandale. In the latest company-slide exposé by VR-Zone, details emerge of yet another iteration to Intel's plans: Clarkdale. Correct spelling is Clarkdale and Arrandale by the way (not Clarksdale or Arandale).

While it is unclear at this point, if this chip, like the Arrandale (32 nm CPU + 32 nm IGP), is built to be deployed on both desktop and mobile platforms, the reason behind its development gains clarity. The Ibex-Peak platform design by Intel, be it dual-core or quad-core, consists of a standard multi-chip module (MCM)-based design, where two dice populate a package: the central processor, and the northbridge. The design gives the company flexibility by introducing a degree of modularity. After scrapping plans of a full-on processor built on the 45 nm high-K manufacturing process, Intel seems to have realised that its foundries won't be able to cater to many designs based on the 32 nm process initially, at once. Taking advantage of the MCM design, Intel is working on this new chip: Clarkdale, which consists of the processor die built on the 32 nm second-generation high-K process, with the northbridge being built on the existing 45 nm process. This design helps evade the manufacturing constraints Intel might have initially. The northbridge die will feature an integrated graphics processor that connects to its output using the flexible-display interface. With this, Intel is looking to bring in immediate and cost-cutting to the extant feasible.


Source: VR-Zone

Having reacted rather sharply to the ongoing global economic slump by planning massive workforce and production cuts, one would expect Intel to be conservative with its development potential. In a contradiction to just that, a recent conversation EETimes had with Mark Bohr, director of Intel's technology and manufacturing group, the director said that the company is on course with its plans to introduce the newer 32 nm silicon fabrication technology by late 2009.

"The 32 nm technology is getting ready to go into the manufacturing phase, we are lining up fabs to support it and we expect great demand. We are on track for shipping products in the fourth quarter and have 22 nm technology in development for 2011" said Mr. Bohr. The conversation previewed some of the papers Intel plans to present at the International Solid-State Circuits Conference that convenes next week.

Intel follows a "tick-tock" model of product development cycle, wherein, the company designs new microprocessor designs and silicon fabrication technologies in alternation. In each cycle, an architecture gets to be made on at least two successive fabrication technologies before itself being succeeded by a newer design. Currently Intel employs the 45 nm High-K metal gate manufacturing technology, on which it introduced later variants of the Core 2 series CPUs, and has introduced its Nehalem architecture, with Core i7 being its first commercial implementation.

Source: EETimes

Grappling with a deteriorating world economy, and overstocked inventories with current-generation Core 2 platforms, Intel seems to have had a change of plans with regards to its dual-core Nehalem-derivatives. Company roadmaps originally pointed at two chips, codenamed Havendale and Auburndale to be the dual-core MCM implementations of the Nehalem architecture, for desktops and notebooks respectively. The "MCM" (multi-chip module) part comes to light in the way the chips were originally conceived: two dice on a package, one holding the CPU complex and the other holding the northbridge, consisting of a memory controller, PCI-Express root complex, and a graphics controller.

Theo Valich, noted industry commentator, in his latest blog post in Theo's Bright Side of IT, mentions that Intel scrapped Havendale and Auburndale in its conceived form. The two were set to make possible Intel Core i4 and i3 SKUs. Instead, Intel is working to push forward the launch of their common successor by six months: the Arandale core. Arandale features in the future series of Nehalem-derived processors to be built on the 32nm high-K silicon process, slated for 2010. Arandale from all that is known thus far is the dual-core Nehalem implementation on 32nm lithography, apart from speculation of it holding a higher amount of L3 cache: possibly 6 MB against 4 MB on the Havendale/Auburndale. The Arandale core was originally slated for "back to school" season, 2010 (around September~October). After rescheduling the launch, it could arrive by March.


Source: Theo's Bright Side of IT

Intel Corporation has completed the development phase of its next-generation manufacturing process that further shrinks chip circuitry to 32 nanometers (a billionth of a meter). The company is on track for production readiness of this future generation using even more energy-efficient, denser and higher performing transistors in the fourth quarter of 2009. Intel will provide a multitude of technical details around the 32nm process technology along with several other topics during presentations at the International Electron Devices meeting (IEDM) next week in San Francisco.

IBM, Chartered Semiconductor Manufacturing, Samsung Electronics, and ARM today announced they will develop a comprehensive 32 nanometer (nm) and 28nm Systems-on-a-Chip (SoCs) design platform based on high-k metal-gate (HKMG) technology from the IBM-led joint-development alliance. Under this multi-year collaboration, ARM will develop and license a design platform of physical intellectual property (IP) including logic, memory and interface products for the Common Platform technology alliance of IBM, Chartered and Samsung for distribution to their customers.

IBM and its chip development partners announced today that they've developed the first functional 22nm silicon fabricated SRAM cell. This puts them ahead of Intel, which had announced its technological entry into the 32 nm domain in September, 2007. SRAM is usually the first semiconductor device a chip-maker tests a new fabrication-process on, before working on microprocessors. These devices were developed and manufactured by AMD, Freescale, IBM STMicroelectronics, Toshiba and the College of Nanoscale Science and Engineering (CNSE). They were built in the conventional 6-transistor design and on a 300 mm wafer. This level of miniaturization made the SRAM cell shrink to a mere 0.1 sq. μm, compare this to the SRAM cells that go into making caches on the 45 nm Intel processors, 0.346 sq. μm.

Responding to IBM and its development partners that took the lead in the nm battle by announcing the availability of a high-k and metal-gate 32nm offering, Taiwan Semiconductor Manufacturing (TSMC) today outlined more details about its 32nm process. Rick Tsai, president and chief executive of the company said "We will have high-k and metal-gate at 32nm," during a keynote at the 2008 Technology Symposium. Jack Sun, vice president of research and development, also indicated that TSMC will develop a third-generation triple-gate oxide technology for its 32nm low-power process. For its 32nm high-performance process, TSMC will offer a high-k and metal gate technology, Sun added.

Source: EETimes

IBM and its joint development partners - Chartered Semiconductor Manufacturing, Freescale, Infineon Technologies AG, Samsung Electronics, STMicroelectronics N.V. and Toshiba Corporation - today announced that they have collectively demonstrated significant performance and power consumption advantages over industry standards by using a breakthrough material known as "high-k/metal gate" (HKMG) on silicon manufactured at IBM's state-of-art 300 millimeter (mm) semiconductor fabrication facility in East Fishkill, N.Y. With this achievement the joint development partners are now ready for early customer engagements.